hcts161ams Intersil Corporation, hcts161ams Datasheet

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hcts161ams

Manufacturer Part Number
hcts161ams
Description
Radiation Hardened Synchronous Counter
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• Minimum LET for SEU Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCTS161AMS high-reliability high-speed presettable
four-bit binary synchronous counter features asynchronous reset
and look-ahead carry logic. The HCTS161AMS has an active-low
master reset to zero, MR. A low level at the synchronous parallel
enable, SPE, disables counting and allows data at the preset
inputs (P0 - P3) to load the counter. The data is latched to the
outputs on the positive edge of the clock input, CP. The
HCTS161AMS has two count enable pins, PE and TE. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
The HCTS161AMS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS161AMS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS161ADMSR
HCTS161AKMSR
HCTS161AD/Sample
HCTS161AK/Sample
HCTS161AHMSR
Day (Typ)
-VIL = 0.8V Max
-VIH = VCC/2V Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
HCTS161AMS
1
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
SCREENING LEVEL
Pinouts
GND
MR
CP
PE
P0
P1
P2
P3
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
CP
PE
P0
P1
P2
P3
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Synchronous Counter
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
File Number
PACKAGE
TC
Q0
Q1
Q2
Q3
TE
SPE
VCC
518888
2144.2
TC
Q0
Q1
Q2
Q3
TE
SPE
VCC

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hcts161ams Summary of contents

Page 1

... P3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count ...

Page 2

... Functional Test VIL = 0.8V, (Note 3) NOTES: 1. All voltages reference to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS161AMS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 3

... CIN Pulse Width Time CP TW Pulse Width Time MR TW Setup Time TSU Setup Time TSU Setup Time SPE to CP TSU Hold Time TSU Specifications HCTS161AMS GROUP (NOTES SUB- CONDITIONS GROUPS TEMPERATURE 9 10, 11 +125 9 10, 11 +125 ...

Page 4

... VCC = 4.5V, VIH = 3.0V, VIL = Propagation Delay TPHL5 VCC = 4.5V, VIH = 3.0V, VIL = NOTES: 1. All voltages referenced to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCTS161AMS (NOTE 1) CONDITIONS TEMPERATURE VCC = 4.5V, VIH = 4.5, VIL = 0.0V, +125 VCC = 4.5V, VIH = 4.5, VIL = 0.0V, +125 VCC = 4 ...

Page 5

... Group D NOTE: 1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. Specifications HCTS161AMS GROUP B SUBGROUP DELTA LIMIT 5 5 -15 Hour TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS ...

Page 6

... Each pin except VCC and GND will have a resistor of 10k 2. Each pin except VCC and GND will have a resistor of 1k TABLE 9. IRRADIATION TEST CONNECTIONS OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. HCTS161AMS 0.5V VCC = 6V 0. ...

Page 7

... Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HCTS161AMS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs. min., o +125 C min., Method 1015 ...

Page 8

... TH TSU TW INPUT CP VIH VS VIL TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS161AMS Propagation Delay Load Circuit DUT TPHL CL = 50pF RL = 500 UNITS Load Circuit DUT CL = 50pF RL = 500 UNITS TEST ...

Page 9

... Metallization Mask Layout P0 (3) P1 (4) P2 (5) P3 (6) PE (7) NOTE: The die diagram is a generic plot form a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCTS161A is TA14446A. HCTS161AMS HCTS161AMS CP MR VCC (2) (1) (16) (8) (9) ...

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