k4h280438d Samsung Semiconductor, Inc., k4h280438d Datasheet - Page 41

• Manufacturer Part Number: k4h280438d
• Description: 128mb D-die X4/8 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

128Mb D-die(x4/8) DDR SDRAM
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
2. Timing patterns
I
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
2. Timing patterns
DD7A
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK,Read with autoprecharge
-DDR333(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK,Read with autoprecharge
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
changing. lout = 0mA
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
: Operating current: Four bank operation
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REV. 0.3 Jan.31. 2001