k4m511633c Samsung Semiconductor, Inc., k4m511633c Datasheet - Page 9

• Manufacturer Part Number: k4m511633c
• Description: 8m X 16bit X 4 Banks Mobile Sdram In 54fbga
• Manufacturer: Samsung Semiconductor, Inc.

SIMPLIFIED TRUTH TABLE
NOTES :
1. OP Code : Operand Code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are the same as CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
K4M511633C - R(B)N/G/L/F
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down
Mode
DQM
No Operation Command
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
X
H
H
X
X
X
X
X
H
H
X
L
L
L
CS
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
RAS
9
X
H
H
H
H
H
H
L
L
X
L
L
X
V
X
X
X
V
X
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
WE
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
DQM BA0,1 A10/AP
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
V
V
V
X
Mobile SDRAM
OP CODE
H
H
H
Row Address
L
L
L
X
X
X
X
X
X
X
A11, A12
A9 ~ A0
Address
(A0~A8)
Address
(A0~A8)
Column
Column
X
March 2006
Note
1, 2
4, 5
4, 5
3
3
3
3
4
4
6
7