at572d940hf-cl ATMEL Corporation, at572d940hf-cl Datasheet - Page 24

• Manufacturer Part Number: at572d940hf-cl
• Description: Diopsis 940hf Arm926ej-s Plus Gflops
• Manufacturer: ATMEL Corporation

5.9.1
5.9.2
5.10
Table 5-1.
24
0x0000 0000
0x1000 0000
0x9000 0000
0xF000 0000
Address
Start
Memory Mapping
AT572D940HF Preliminary
Static Memory Controller (SMC)
Synchronous Dynamic RAM Controller (SDRAMC)
D940HF Global Memory Map
Size (MB)
8 x 256
6 x 256
256
256
The SMC gives to the AHB enabled Hosts the capability to access to the following type of exter-
nal memories: SRAM, Nor-Flash, EPROM, EEPROM.
The additional NAND LOGIC also provides the SMC with the capability to interface the Smart-
Media removable non-volatile memory cards and the Nand FLASH memory chips.
The additional Compact Flash logic provides the SMC with the capability to interface the Com-
pact Flash removable non-volatile memory cards.
The SDRAMC provides the interface to an external 16-bit or 32-bit SDRAM device.
The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048.
It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The SDRAMC supports a read or write burst length of one location. It does not support byte
read/write bursts or half-word write bursts. It keeps track of the active row in each bank (avoiding
precharge and active when, changing bank, the old row is accessed), thus maximizing SDRAM
performance, e.g., the application may be placed in one bank and data in the other banks. So it
is advisable to avoid accessing different rows in the same bank in order to optimize
performance.
The maximum number of SDRAM locations that can be randomly accessed without penalty
cycles (precharge, active) corresponds to the device row size x the number of banks. The
SDRAMC can support row size up to 2048 locations and 4 banks: hence maximum 8K locations
can be accessed without penalties. Anyway, typical SDRAM row size are 512/256 locations so
maximum 2K/1K locations can be accessed without penalties.
The present section describes the memory mapping of ARM9System.
Table 5-1
ARM9-I
mst # 0
shows the D940HF global memory map:
ARM9-D
Internal Peripherals (See
mst #1
External Memories (See
mst # 2
Internal Memories (See
PDC
Undefined (Abort)
Table 5-4
masters
magicV
mst # 3
Table 5-2
)
Table 5-3
)
mst # 4
USB
)
mst # 5
ETH
7010AS–DSP–07/07
m-JTAG
mst # 6