tsc695fl ATMEL Corporation, tsc695fl Datasheet - Page 2

• Manufacturer Part Number: tsc695fl
• Description: Sparc Processor
• Manufacturer: ATMEL Corporation

3. Floating-Point Compare Single or Double Instruction followed by specific IU Instruction followed by Float-
2
ing-Point Store Double Instruction
If a floating-point compare single or double instruction (FCMPS, FCMPES, FCMPD or FCMPED) is immediately followed by
one of the OR, ORcc, ORN, ORNcc, SRL, TADDccTV, Ticc, RDWIM or WRWIM instruction, and the next instruction is a
floating-point store double (STDF) of any floating-point register (involved or not in the floating-point compare single or
double instruction), the stored floating-point double value is corrupted.
Data corruption happens as follows: the program location of the floating-point compare single or double instruction is
written into memory at the effective store address instead of the expected most significant word in the even-numbered
floating-point source register.
The floating-point registers involved in the floating-point store double operation are not corrupted, nor any other float-
ing- point register.
The error case appears when any of the four following sequences of instructions is present:
–
–
–
–
Workarounds
If direct control over assembly language is possible, simply insert a NOP after the floating-point compare single or dou-
ble instruction:
–
–
–
Case 1:
Case 2:
Case 3:
Case 4:
Case 1:
Case 2:
Case 3:
Note:
FCMPS
IUop
STD
FCMPES %fx,%fy
IUop
STD
FCMPD
IUop
STD
FCMPED %fx,%fy
IUop
STD
FCMPS
NOP
IUop
STD
FCMPES %fx,%fy
NOP
IUop
STD
FCMPD
NOP
1. IUop is one of OR, ORcc, ORN, ORNcc, SRL, TADDccTV, Ticc, RDWIM or WRWIM instructions,
(1)
(1)
(1)
(1)
(1)
(1)
whatever the operands are.
%fx,%fy
%fz,[address]
%fz,[address]
%fx,%fy
%fz,[address]
%fz,[address]
%fx,%fy
%fz,[address]
%fz,[address]
%fx,%fy
4280D–AERO–07/06