adsst-21065lks-240 Analog Devices, Inc., adsst-21065lks-240 Datasheet - Page 12

• Manufacturer Part Number: adsst-21065lks-240
• Description: High End, Multichannel, 32-bit Floating-point Audio Processor
• Manufacturer: Analog Devices, Inc.

SST-Melody-SHARC
SOFTWARE ARCHITECTURE
The audio DSP chipsets from Analog Devices allows designers
to make value additions to product features working off the high
end base functionality that they are provided with. The
SST-Melody-SHARC
•
•
The executive kernel gets executed as soon as booting takes place.
The hardware resources are initialized in the beginning. The
command buffer and general-purpose programmable flag pins
are initialized. Various data buffers and memory variables are
initialized. Interrupts are programmed and enabled. Then, definite
signatures are written “Command buffer” to inform the host
that
Once commands are issued by host micro, they are executed
and appropriate action takes place. Decoding is handled by issuing
appropriate commands by host micro.
The kernel communicates with library module for a particular
algorithm in a definite way. The details are found in the specific
implementation documents. As the kernel is modular, it is easy to
customize to different hardware platforms. Most of the time, the
user needs to change the initialization code to suit the codec chosen.
SST-MELODY-SHARC GENERAL DESCRIPTION
The SST-Melody-SHARC is a powerful member of the
SHARC family of 32-bit processors optimized for cost sensitive
applications. The SHARC—Super Harvard Architecture—offers
the highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSPs in the
industry that offer both fixed and floating-point capabilities
without compromising precision or performance.
Fabricated in a high speed, low power CMOS process, 0.35 µm
technology, the SST-Melody-SHARC offers the highest perfor-
mance by a 32-bit DSP—66 MIPS (198 MFLOPS). With its
on-chip instruction cache, the processor can execute every instruction
in a single cycle. Table I lists the performance benchmarks for
the SST-Melody-SHARC.
The SST-Melody-SHARC SHARC combines a floating-point
DSP core with integrated, on-chip system features, including a
544 Kbit SRAM memory, host processor interface, DMA control-
ler, SDRAM controller, and enhanced serial ports.
INPUT STREAM
The executive kernel has the following functions:
• Power up hardware initialization
• Serial port management
• Automatic stream detect
• Automatic code load
• Command processing
• Interrupt handling
• Data buffer management
• Calling library module
• Status report
Executive kernel
Algorithm as library module
SST-Melody-SHARC
Figure 1. Software
software has the following parts:
EXECUTIVE KERNEL
DECODING LIBRARY
is ready to receive the commands.
OUTPUT STREAM
–12–
Benchmark
Cycle Time
1024-Pt Complex FFT
Matrix Multiply (Pipelined)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide Y/X
Inverse Square Root (1/
DMA Transfers
(Radix 4, with Digit Reverse)
[3
[4
CLOCK
RESET
Figure 2. SST-Melody-SHARC Single-Processor System
01
3]
4]
[3
[4
CONTROL
SPORT0
TX0_A
TX0_B
RX0_A
RX0_B
SPORT1
TX1_A
TX1_B
RX1_A
RX1_B
Table I. Performance Benchmarks
CLKIN
ID1-0
RESET
SST-Melody-
1]
1]
SHARC
#1
ADDR23-0
DATA31-0
SDCLK1-0
√
SDCKE
SDA10
x)
MS3-0
SDWE
SBTS
REDY
BMS
DQM
ACK
HBR
HBG
CPA
RAS
CAS
BR2
BR1
WR
SW
RD
CS
Timing
15.00 ns
0.274 ns
135 ns
240 ns
15 ns
60 ns
90 ns
135 ns
264 MBytes/sec
CS
ADDR
DATA
ADDR
DATA
CS
CS
ADDR
DATA
WE
RAS
CAS
DQM
CLK
CKE
A10
PROCESSOR
(OPTIONAL)
(OPTIONAL)
HOST
(OPTIONAL)
SDRAM
EPROM
1
4
6
Cycles
1
18221
9
16
9
BOOT
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