mc54hc589 Freescale Semiconductor, Inc, mc54hc589 Datasheet - Page 6

• Manufacturer Part Number: mc54hc589
• Description: 8-bit Serial Parallel-input/serial-output Shift Register With 3-state Output
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
data latch on the rising edge of the Latch Clock input.
S A (Pin 14)
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register ac-
cepts parallel data from the data latch.
MC54/74HC589
Parallel data inputs. Data on these inputs are stored in the
Serial data input. Data on this input is shifted into the shift
Shift register mode control. When a high level is applied to
DEVICE
UNDER
TEST
* Includes all probe and jig capacitance
OUTPUT
PIN DESCRIPTIONS
TEST POINT
TEST CIRCUIT
Figure 9.
C L *
1 k
3–6
Shift Clock (Pin 11)
shifts data on the serial data input into the shift register and
data in stage H is shifted out Q H , being replaced by the data
previously stored in stage G.
Latch Clock (Pin 12)
loads the parallel data on inputs A–H into the data latch.
Output Enable (Pin 10)
forces the Q H output into the high impedance state. A low
level enables the output. This control does not affect the
state of the input latch or the shift register.
OUTPUT
Q H (Pin 9)
of the shift register. This is a 3–state output.
Serial shift clock. A low–to–high transition on this input
Data latch clock. A low–to–high transition on this input
Active–low output enable A high level applied to this pin
Serial data output. This pin is the output from the last stage
CONNECT TO V CC WHEN
TESTING t PLZ AND t PZL .
CONNECT TO GND WHEN
TESTING t PHZ AND t PZH .
High–Speed CMOS Logic Data
DL129 — Rev 6