pc7410 ATMEL Corporation, pc7410 Datasheet
pc7410
Related parts for pc7410
pc7410 Summary of contents
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... New features have been developed to make latency equal for double-precision and single-precision floating-point operations involving multiplication. Additionally, in mem- ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface. ) ™ ...
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... CBGA Upscreenings Based on Atmel Standards • Full Military Temperature Range (T Industrial Temperature Range (T • CI-CGA Package Version, HiTCE Package Version Ceramic Ball Grid Array Ceramic Ball Grid Array PC7410 2 = -55°C, +125°C -40°C, +110° suffix CBGA 360 ...
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Instruction Unit Fetcher Additional features Time Base 64-entry BTIC/512-entry BHT Counter/Decrementer Clock Multiplier Instruction JTAG/COP Interface Queue Thermal/Power Management 6-word Performance Monitor 2 Instructions 64-bit (2 Instructions) Reservation Reservation Reservation Station Station Station VR File 6 Rename Buffers Integer Vector ...
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... General Parameters Features PC7410 4 Table 1 provides a summary of the general parameters of the PC7410. Table 1. Device Parameters Parameter Description Technology 0.18 µm CMOS, six-layer metal Die size 6.32 mm × 8.26 mm (52 mm Transistor count 10.5 million Logic design Fully-static Packages Surface-mount 360 ceramic ball grid array (CBGA) Surface mount 360 high coefficient of thermal expansion ...
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... Big- and little-endian byte addressing supported – Misaligned little-endian supported – Supports FXU, FPU, and AltiVec load/store traffic – Complete support for all four architecture AltiVec DST streams • Level 1 (L1) Cache Structure – 32K 32-byte line, 8-way set associative instruction cache (iL1) PC7410 5 ...
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... PC7410 6 – 32K 32-byte line, 8-way set associative data cache (dL1) – Single-cycle cache access – Pseudo least-recently-used (LRU) replacement – Data cache supports AltiVec LRU and transient instructions algorithm – Copy-back or write-through data cache (on a page-per-page basis) – Supports all PowerPC memory coherency modes – ...
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... Testability – LSSD scan design – IEEE 1149.1 JTAG interface – Array built-in self test (ABIST) – factory test only – Redundancy on L1 data arrays and L2 tag arrays • Reliability and Serviceability – Parity checking on 60x and L2 cache buses PC7410 7 ...
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... Signal Description PC7410 8 Figure 2. PC7410 Microprocessor Signal Groups BR 1 Address BG Arbitration 1 ABB/AMON[0] 1 Address TS 1 Start A[0:31] 32 Address AP[0:3] Bus 4 TT[0:4] 5 TBST 1 TSIZ[0:2] 3 Transfer Attribute GBL CHK 1 AACK 1 Address Termination ARTRY 1 DBG 1 Data DBWO, DTI(0) 1 Arbitration DBB, DMON(0) 1 D[0:63] 64 Data DP[0:7] 8 Transfer DTI(2) ...
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... V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV -0.3 to 2.6V. 2141D–HIREL–02/04 This drawing describes the specific requirements for the microprocessor PC7410 in compliance with Atmel-Grenoble standard screening ...
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... GND - 0.7V The PC7410 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7410 “core” voltage must always be provided at nominal voltage (see Table 4 for actual recommended core voltage). Volt- age to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3 ...
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... These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV value of 2.5V ±100 mV for BVSEL = 1. 3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET. 4. Not supported for N spec with V 2141D–HIREL–02/04 (1) ...
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... See “Thermal Management Information” on page 13 for more details about thermal management. The board designer can choose between several commercially available heat sink types to place on the PC7410. For exposed-die packaging technology as in Table 5, the intrinsic conduction thermal resistance paths are shown in Figure 4. ...
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... Figure 5. CBGA Package Cross-section with Heat Sink Options Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Printed-Circuit Board Radiation Convection Heat Sink Thermal Interface Material Die Junction Die/Package Package/Leads Radiation Convection Option PC7410 13 ...
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... Adhesives and Thermal Interface Materials PC7410 14 A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 6 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure ...
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... Figure should be maintained less than the j ) may range from 30° may be in the range of 5° int of 5°C, a CBGA package θ = 0.03, and a power obtained: j ⁄ θ ) × 1,0° PC7410 ) is typically about ) ver ...
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... PC7410 16 Figure 7. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity 0.5 1 Assuming an air velocity of 0.5 m/s, the effective R ( ⁄ 30°C + 5°C + 0,03° 1,0° resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating temperature of the component. ...
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... Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP) ...
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... Power Dissipation PC7410 18 Table 8. Power Consumption for PC7410 (1.8V) Power Mode 400 MHz Core power supply 1.5V Full-On Mode (1)(3) Typical 2.92 (1)(2)(4)(5) Maximum 6.6 Doze Mode (1)(2)(5) Maximum 3.6 Nap Mode (1)(2)(5) Maximum 1.35 Sleep Mode (1)(2)(5) Maximum 1.3 Sleep Mode - PLL and DLL Disabled (1)(3) Typical 600 (1)(2)(5) Maximum 1.1 Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not ...
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... OV + 0 0 0.3 DD -0.3 0.2 -0.3 0.4 -0.3 0.4 – 20 – 35 – 70 – 20 – 35 – 70 (L2)OV - 0.45 – DD 1.7 – 2.4 – – 0.45 – 0.4 – 0.4 – 6.0 is the reference for the L2 bus signals. and L2OV must vary in the same direction (for DD DD PC7410 Unit + 0 0 µA µ ...
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... PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. PC7410 20 After fabrication, parts are sorted by maximum processor core frequency as shown in “ ...
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... SYSCLK CVIH VM VM CVIL Note Midpoint Voltage (OV DD Table 11 provides the processor AC timing specifications for the PC7410 as defined in Figure 10 and Figure 11. Timing specifications for the L2 bus are provided in “L2 Bus AC Specifications” on page 26. ( 100 mV (7)(8) (7)(12) for outputs ...
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... All Outputs (except TS, ABB, ARTRY, DBB) t All Outputs KHOE (except TS, ABB, ARTRY, DBB) TS, t ABB/AMON[0], KHTSV DBB/DMON[0] ARTRY, t KHARV SHD0, SHD1 PC7410 22 period, to ensure that another master asserting ABB, or DBB on the following SYSCLK IVKH t IXKH t KHOX t t KHABPZ t KHTSV t KHTSX ...
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... L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of the PC7410 will be a function of the AC timings of the PC7410, the AC timings for the SRAM, bus loading and printed circuit board trace length. ...
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... L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis. PC7410 24 L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency) ...
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... Figure 12. L2CLK_OUT Output Timing Diagram L2 Single-Ended Clock Mode L2CLK_OUTA VM L2CLK_OUTB VM VM L2SYNC_OUT L2 Differential Clock Mode L2CLK_OUTB VM L2CLK_OUTA VM L2SYNC_OUT Note Midpoint Voltage (L2OV 2141D–HIREL–02/04 t L2CLK t CHCL L2CLK t CHCL /2) DD PC7410 t t L2CR L2CF t L2CSKW VM 25 ...
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... Figure 13. L2 Bus Input Timing Diagram L2SYNC_IN L2 Data and Data Parity Inputs Note Midpoint Voltage (L2OV PC7410 26 Table 13 provides the L2 bus interface AC timing specifications for the PC7410 as defined in Figure 13 and Figure 14 for the loading conditions described in Figure 15 L2AV DD DD 100mV or L2OV = 1.8V 100mV ± ...
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... Figure 14. L2 Bus Output Timing Diagram L2SYNC_IN All Outputs L2DATA BUS Note Midpoint Voltage (L2OV Figure 15. AC Test Load for the L2 Interface Output 2141D–HIREL–02/ L2CHOV t L2CHOX / 50 50: t L2CHOZ L2OV /2 DD PC7410 27 ...
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... IEEE 1149.1 AC Timing Specifications PC7410 28 Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 16, Figure 17, Figure 18 and Figure 19. Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) mended Operating Conditions (see Table 4) Symbol Parameter f TCK frequency of operation TCLK t TCK cycle time TCLK t TCK clock pulse width measured at OVDD/2 ...
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... VM = Midpoint Voltage (OV DD 2141D–HIREL–02/04 t TRST VM / JLDV t JLDX t JLDZ Output Data Valid / JLOV t JLOX t JLOZ Output Data Valid / DVJH t DXJH Input Data Valid Output Data Valid VM t IVJH t IXJH Input Data Valid Output Data Valid PC7410 29 ...
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... Preparation for Delivery Handling Package Mechanical Data Parameters PC7410 30 MOS devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: • ...
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... BGA360 Package 2141D–HIREL–02/04 Figure 21, Figure 22, Figure 23 and Figure 24 show top views of the packages available for the PC7410. Note that these drawings are not to scale. Figure 21. Top View of 360-Ball CBGA and 360-Pin CI-CGA Packages Pin A1 Index Figure 22. Top View of 360-pin CBGA and CI-CGA Packages ...
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... Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages Signal Name Pin Number A[0:31] A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 AACK N3 (12) ABB L7 (12) AMON[0] AP[0:3] C4, C5, C6, C7 ARTRY ...
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... Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued) Signal Name Pin Number DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 DL[0:31] M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, ...
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... To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV (selects 2.5V), GND (selects 1.8V HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus only support the 1.8 and 2.5 options (see Table 3). the default selection if BVSEL and/or L2VSEL is left unconnected is 2.5V 4 ...
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... Reuses PC750’s DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively). 11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OV 12. Output only for PC7410, was I/O for PC750. 13. Enhanced mode only. 14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250Ω ...
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... B Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array PC7410 C6-2 ...
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... Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array 2141D–HIREL–02/ C6-2 12X C1-1 C6-1 J2 C1-2 0.15 A 0. C2-2 C2 171819 0 0.15 C PC7410 ...
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... Figure 27. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package PIN A1 INDEX Parameter Min A 3.4 A1 1.545 A2 1. 0. PC7410 TOP VIEW 1213141516 ...
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... The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7410; see “Clock AC Specifications” on page 20 for valid SYSCLK, core, and VCO frequencies. ...
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... Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported or not tested for by the PC7410; see “L2 Clock AC Specifications” on page 23 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. ...
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... V DD The notes in Table 2 contain cautions about the sequencing of the external bus voltages and core voltage of the PC7410 (when they are different). These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and excessive current can flow through these diodes ...
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... Power and ground connections must be made to all external V GND pins of the PC7410. See “L2 Clock AC Specifications” on page 23 for a discussion of the L2SYNC_OUT and L2SYNC_IN signals. The PC7410 60x and L2 I/O drivers are characterized over process, voltage and tem- perature. To measure external resistor is connected from the chip pad GND ...
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... R 37.3 - 55.3 P The PC7410 requires pull-up resistors (1 kΩ–5 kΩ) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7410 or other bus masters. These pins are: TS, ARTRY, SHDO, SHD1. ...
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... In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on GBL. Note that the PC7410 will only snoop transactions when GBL is asserted. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus ...
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... The QACK signal shown in Figure 32 is usually connected to the PCI bridge chip in a system and is an input to the PC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7410 must see this signal asserted (pulled down) ...
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... Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7410. Connect pin 5 of the COP header Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK. ...
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... TRST ensures that the JTAG scan chain is initialized during power- JTAG interface cable is not attached attached responsible for driving TRST when needed. . Used on several emulator products. Useful for PC7410 ...
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... PC7410 48 The COP header shown in Figure 32 adds many benefits – breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. ...
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... Atmel customers using or selling these products for use in such applications their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. PC7410 Validity Before design phase Valid during the design phase ...
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... Section “PLL and DLL Power Supply Filtering” on page 40 — revised section for HCTE package. Added text and figure for AV filter for the CBGA package. DD Section “Pull-up Resistor Requirements” on page 43 — removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST from snooped transfer attribute list. TBST is an output and is not snooped. PC7410 50 PC (X) 7410 V ...
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... Internal Package Conduction Resistance ................................................... 13 Thermal Management Information .............................................................. 13 Adhesives and Thermal Interface Materials ................................................ 14 Power Consideration .......................................................................................... 17 Power Management..................................................................................... 17 Power Dissipation ....................................................................................... 18 Electrical Characteristics.................................................................. 19 Static Characteristics .......................................................................................... 19 Dynamic Characteristics ..................................................................................... 20 Clock AC Specifications .............................................................................. 20 Processor Bus AC Specifications ............................................................... 21 L2 Clock AC Specifications ......................................................................... 23 L2 Bus AC Specifications ............................................................................26 IEEE 1149.1 AC Timing Specifications....................................................... 28 Preparation for Delivery .................................................................... 30 Handling .............................................................................................30 PC7410 i ...
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... PC7410 [Preliminary] ii Package Mechanical Data .................................................................30 Parameters .........................................................................................................30 Pin Assignment.................................................................................. 31 BGA360 Package ............................................................................................... 31 Clock Selection ..................................................................................39 System Design Information ..............................................................40 PLL and DLL Power Supply Filtering.................................................................. 40 Power Supply Voltage Sequency ....................................................................... 41 Decoupling Recommendations........................................................................... 42 Connection Recommendations............................................................................42 Output Buffer DC Impedance ............................................................................. 42 Pull-up Resistor Requirements ........................................................................... 43 JTAG Configuration Signals ............................................................................... 45 Definitions ..........................................................................................49 Datasheet Status Description ............................................................................. 49 Life Support Applications ...
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... PC7410 iii ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...