ppc405gpr-3kb400z Applied Micro Circuits Corporation (AMCC), ppc405gpr-3kb400z Datasheet - Page 49

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ppc405gpr-3kb400z

Manufacturer Part Number
ppc405gpr-3kb400z
Description
Power Pc 405gpr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
Revision 2.05 – March 24, 2008
I/O Specifications—Group 1
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV
AMCC
Trace
[TS1E]
[TS2E]
[TS1O]
[TS2O]
[TS3]
[TS4]
[TS5]
[TS6]
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
and I/O L is specified at 0.4 V.
Signal
Data Sheet
Setup Time
(T
IS
na
min)
Input (ns)
Hold Time
(T
DD
IH
na
(Sheet 3 of 3)
and I/O L is specified at 0.1OV
min)
Valid Delay
(T
PT
OV
C
/2+0.7
max)
405GPr – Power PC 405GPr Embedded Processor
Output (ns)
Hold Time
(T
PT
OH
C
/2-0.5
min)
DD
. For all other interfaces, I/O H is specified at 2.4 V
Output Current (mA)
(min)
I/O H
10.3
(min)
I/O L
7.1
TrcClk
Clock
10pF load
clk/data
Notes
on
49

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