ucq5832ep Allegro MicroSystems, Inc., ucq5832ep Datasheet - Page 5

• Manufacturer Part Number: ucq5832ep
• Description: Bimos Ii 32-bit Serial Input Latched Driver
• Manufacturer: Allegro MicroSystems, Inc.

A. Minimum Data Active Time Before Clock Pulse
B. Minimum Data Active Time After Clock Pulse
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
L = Low Logic Level
STROBE
OUTPUT
ENABLE
Serial
Data
Input Input I
DATA IN
H
L
X
CLOCK
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
OUT
(Data Set-Up Time) .......................................................................... 75 ns
(Data Hold Time) ............................................................................. 75 ns
Output Transition ........................................................................... 500 ns
Clock
N
(V
DD
H
L
R
X
P
1
1
1
Shift Register Contents
= 5.0 V, Logic Levels are V
A
H = High Logic Level
I
R
R
R
X
P
2
2
1
1
2
C
B
TIMING CONDITIONS
I
R
R
R
X
P
3
3
2
2
3
D
...
...
...
...
...
...
E
I
R
R
R
X
P
N-1
N-1
N-2
N-2
N-1
F
I
R
R
R
X
P
N
X = Irrelevant
G
N-1
N-1
N
N
Output
Serial
Data
R
R
R
X
P
DD
N
N-1
N-1
N
and Ground)
P = Present State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Strobe
Input
TRUTH TABLE
H
L
Dwg. No. A-12,276A
I
R
P
X
1
1
1
Latch Contents
I
R
P
X
2
2
2
R = Previous State
I
R
P
X
3
3
3
...
...
...
...
ferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
transferred to its respective latch when the
STROBE is high (serial-to-parallel conver-
sion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are con-
trolled by the state of the latches.
I
R
P
X
N-1
N-1
N-1
Serial Data present at the input is trans-
Information present at any register is
When the OUTPUT ENABLE input is low,
P
R
I
X
N
N
N
Enable
Output
Input
H
L
I
P
H H H ... H
1
1
I
P
2
Output Contents
2
I
P
3
3
... I
... P
N-1
N-1
I
P
N
H
N