mt9v011ia9stces aptina, mt9v011ia9stces Datasheet - Page 14
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mt9v011ia9stces
Manufacturer Part Number
mt9v011ia9stces
Description
Mt9v011 1/4-inch Vga Digital Image Sensor
Manufacturer
aptina
Datasheet
1.MT9V011IA9STCES.pdf
(29 pages)
Two-Wire Serial Interface Sample Read and Write Sequences
16-Bit Write Sequence
Figure 9:
16-Bit Read Sequence
Figure 10:
PDF:0560901182/Source 6061803135
MT9V011_IBGA_DS - Rev. C 6/10 EN
SDATA
SCLK
SDATA
SCLK
START
START
0xBA ADDR
Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
0xBA ADDR
ACK
A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
will then give an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each 8-bit the image sensor will give an acknowledge bit. All 16
bits must be written before the register will be updated. After 16 bits are transferred, the
register address is automatically incremented, so that the next 16 bits are written to the
next register. The master stops writing by sending a start or stop bit.
A typical read sequence is shown in Figure 10. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register
address is auto-incremented after every 16 bits is transferred. The data transfer is
stopped when the master sends a no-acknowledge bit.
ACK
Reg 0x09
Reg 0x09
ACK
START
0xBB ADDR
ACK
14
MT9V011 1/4-INCH VGA DIGITAL IMAGE SENSOR
0000 0010
ACK
0000 0010
ACK
Aptina reserves the right to change products or specifications without notice.
ACK
1000 0100
©2009 Aptina Imaging Corporation. All rights reserved.
1000 0100
ACK
Preliminary
NACK
STOP
STOP