m395t5263az4-ce68 Samsung Semiconductor, Inc., m395t5263az4-ce68 Datasheet
m395t5263az4-ce68
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m395t5263az4-ce68 Summary of contents
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FBDIMM DDR2 Fully Buffered DIMM 240pin FBDIMMs based on 2Gb A-die 83FBGA with Lead-Free and Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE ...
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... DDR2 Channel .................................................................................................................12 3.2 SMBus Slave Interface ..................................................................................................................13 3.3 FBD Channel Latency 3.4 Peak Theoretical Throughput ......................................................................................................................................13 3.5 Hot-add .................................................................................................................................13 3.6 Hot remove .................................................................................................................................13 3.7 Hot replace 4.0 PIN CONFIGUREATION ..............................................................................................................14 5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16 5.1 4GB, 512Mx72 Module - M395T5263AZ4 5.2 8GB, 1Gx72 Module - M395T1K66AZ4 6.0 ELECTRICAL CHARACTERISTICS ............................................................................................18 7.0 CHANNEL INITIALIZATION ........................................................................................................25 .........................................................................................................5 ..............................................................................................6 ............................................................................................................7 ......................................................................................................8 .......................................................................................11 ........................................................................................................13 .........................................................................................16 .......................................................................................... DDR2 SDRAM ...
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FBDIMM Revision History Revision Month Year 1.0 December 2007 1.01 January 2008 1.02 April 2008 - Initial Released. - Typo Correction - Corrected mechanical Dimension DDR2 SDRAM History Rev. 1.03 April 2008 ...
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... Link at 1.5 volt - Channel error detection & reporting - Channel fail over mode support Table 1 : Ordering Information Part Number Density M395T5263AZ4-CE66/F76 4GB M395T5263AZ4-CE68/F78 4GB M395T1K66AZ4-CE66/F76 8GB M395T1K66AZ4-CE68/F78 8GB Note : 1. “Z” of Part number(11th digit) stands for Lead-free products. 2. The last digit stands for AMB. ...
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... FBDIMM GENERALS 2.1 FB-DIMM Operation Overview FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited density build-up as channel speeds increase with memory system having the stub-bus architecture ...
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FBDIMM 2.2 FB-DIMM Channel Frequency Scaling There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. ...
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FBDIMM 2.3 FB-DIMM Clocking Scheme In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account. Thus, clock synchronization is made by using both external reference clock and channel data stream ...
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FBDIMM Figure 5 : FBDIMM Command Encoding & SB Frame Southbound Command Frame Format* Bit aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0 1 aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 ...
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FBDIMM 2.6 Basic Timing Diagram Figure 7 : Basic DRAM Read Data Transfers on FBD 1 2 ACT1 FBD southbound NOP cmd/data NOP DIMM 1 cmd ACT1 DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Figure ...
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FBDIMM Figure 9 : Basic DRAM Write Data Transfers on FBD ACT1 FBD southbound NOP cmd/data NOP DIMM 1 cmd ACT1 DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Figure 10 : ...
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FBDIMM 2.7 Advanced Memory Buffer Block Diagram Figure 11 : Advanced Memory Buffer Block Diagram NORTH 1x2 PLL Ref Clock Reset# Reset Control Command Decoder & CRC Check Thermal Sensor Core Control and CSRs LAI Controller Data CRC Gen & ...
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FBDIMM 2.8 Interfaces Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM- Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory ...
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FBDIMM 3.3 FBD Channel Latency FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by ...
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... SS RFU = Reserved Future Use. * These pin positions are reserved for forwarded clocks to be used in future module implementations ** These pin positions are reserved for future architecture flexibility 1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12, PS9/PS9, SS9/SS9 ...
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... Ground SS The DNU/M_Test pin provides an external connection R/ for testing the margin of Vref which is produced by a voltage divider on the module not intended to be used in normal DNU/M_Test DNU system operation and must not be connected (DNU sys- tem. This test pin may have other features on future card de- signs and if it does, will be included in this specification at that time ...
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... FBDIMM 5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM 5.1 4GB, 512Mbx72 Module - M395T5263AZ4 S1 S0 DQS0 DQS0 DQS9 DM/ NU/ CS DQS DQS RDQS RDQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DQS10 DM/ NU/ CS DQS DQS RDQS RDQS DQ8 I/O 0 DQ9 D1 I/O 1 DQ10 I/O 2 DQ11 I/O 3 DQ12 ...
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... FBDIMM 5.2 8GB, 1Gx72 Module - M395T1K66AZ4 (populated as 2 rank of x4 DDR2 SDRAMs DQS0 DQS0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQS2 DQS2 DM CS DQS DQS DQ16 I/O 0 DQ17 I ...
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FBDIMM 6.0 ELECTRICAL CHARACTERISTICS Table 6 : AbsoIute Maximum Ratings Parameter Voltage on any pin relative Voltage on V pin relative Voltage V pin relative Voltage on V pin ...
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FBDIMM Table 9 : Power specification parameter and test condition Symbol Icc_Idle_0 Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary Channel Disabled Idd_Idle_0 CKE high. Command and address lines stable. DRAM clock active. ...
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... Idd_active_1 5541 P_active_1 16.67 Icc_active_2 3700 Idd_active_2 2700 P_active_2 10.96 Icc_training 4000 Idd_training 2700 P_training 11.43 Note : 1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet. 4GB(M395T5263AZ4) CE68 CF76 (PC2-5300) 2600 3200 1600 1790 7.14 8.44 3400 4200 1600 1790 8.40 10.02 3900 4700 3221 3606 12 ...
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FBDIMM Table Currents TT Description Idle current, DDR2 SDRAM device power down Active power, 50% DDR2 SDRAM BW Table 13 : Reference Clock Input Specifications Parameter Reference clock frequency @3.2 Gb/s (nominal 133.33 MHz) Reference clock frequency ...
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FBDIMM Table 14 : Differential Transmitter Output Specifications Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to -peak output voltage for requ- lar voltage swing Differential peak-to-peak output voltage for small votage swing DC common code output voltage ...
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FBDIMM Table 15 : Differential Receiver Input Specifications Parameter Differential peak-to-peak input voltage for large volt- age swing Maximum single-ended voltage in El condition Maximum single-ended voltage in Ei condition (DC only) Maximum peak-to-peak differential voltage in El condition Single-ended ...
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FBDIMM 11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode specification. For example 200 mV, the maximum AC peak-to peak common mode is the lesser of ...
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FBDIMM 7.0 CHANNEL INITIALIZATION This chapter defines the process of initializing the FBD channel. The FBD initialzation process generally follows the top to bottom se- quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure ...
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... FBDIMM Figure 15 : FBDIMM Physical Dimension -1 (For PCB) : 256Mx8 based 512Mx72 Module (2Rank 5.175 2x DIA. 2.0 +0.1/-0 5.0 0.8 +/- 0.05 2.50 2.50 3.80 MAX 0.178 1.50 DETAIL a M395T5263AZ4 133.35 126.85 d AMB 123 R0.75 120° 1.25 1.00 DETAIL b DETAIL DDR2 SDRAM 2x 2.50 MIN 51 R0.595 1.19 1.19 2.25 R0.595 DETAIL d DETAIL e Rev. 1.03 April 2008 6.0 ...
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... FBDIMM Figure 16 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 256Mx8 based 512Mx72 Module (2Rank) 67 M395T5263AZ4 133.35 51 123 DDR2 SDRAM Units : Millimeters 8.2 max 1.27 ± 0.10 Back 3.0 max Rev. 1.03 April 2008 ...
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... FBDIMM Figure 17 : FBDIMM Physical Dimension -1 (For PCB) : 512Mbx4 based 1Gx72 Module (2Rank 5.175 2x DIA. 2.0 +0.1/-0 5.0 0.8 +/- 0.05 2.50 2.50 3.80 MAX 0.178 1.50 DETAIL a M395T1K66AZ4 133.35 126.85 d AMB 123 R0.75 120° 1.25 1.00 DETAIL b DETAIL DDR2 SDRAM 2x 2.50 MIN 51 R0.595 1.19 1.19 2.25 R0.595 DETAIL d DETAIL e Rev. 1.03 April 2008 6.0 ...
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... FBDIMM Figure 18 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 512Mbx4 based 1Gx72 Module (2Rank) 67 M395T1K66AZ4 133.35 51 123 DDR2 SDRAM Units : Millimeters 8.2 max 1.27 ± 0.10 Back 3.0 max Rev. 1.03 April 2008 ...