hys64v16220gdl-8 Infineon Technologies Corporation, hys64v16220gdl-8 Datasheet - Page 10
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hys64v16220gdl-8
Manufacturer Part Number
hys64v16220gdl-8
Description
So-dimm Sdram Modules
Manufacturer
Infineon Technologies Corporation
Datasheet
1.HYS64V16220GDL-8.pdf
(15 pages)
Notes:
1. All AC characteristics shown are for SDRAM components.
2. AC timing tests have V
3. If clock rising time is longer than 1ns, a time (t
4. If t
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
INFINEON Technologies
An initial pause of 100 s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
point. The transition time is measured between V
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V
..
commands must be given to “wake-up“ the device.
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
levels.
T
is longer than 1ns, a time (t
CLOCK
INPUT
OUTPUT
t
IS
1.4 V
t
t
LZ
IH
t
AC
il
= 0.4 V and V
1.4 V
t
CL
T
t
t
OH
CH
t
-1) ns has to be added to this parameter.
T
t
t
AC
HZ
ih
2.4 V
0.4 V
= 2.4 V with the timing referenced to the 1.4 V crossover
IO.vsd
1.4 V
10
T
HYS64V8200GDL/HYS64V16220GDL
-0.5) ns has to be added to this parameter.
144 pin SO-DIMM SDRAM Modules
ih
and V
il
. All AC measurements assume t
Measurement conditions for
I/O
tac and toh
50 pF
T
=1ns
9.01