hys64d32300hu-6-c Qimonda, hys64d32300hu-6-c Datasheet - Page 16

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hys64d32300hu-6-c

Manufacturer Part Number
hys64d32300hu-6-c
Description
184- Pin Unbuffered Ddr Sdram Modules
Manufacturer
Qimonda
Datasheet
Table 13
Parameter
Address and control input setup
time
Data-out low-impedance time
from CK/CK
Mode register set command cycle
time
DQ/DQS output hold time
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-
refresh command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read command
1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
Internet Data Sheet
(DDR400)
level for signals other than CK/CK, is
T
A
≤ 70 °C
AC Timing - Absolute Specifications for PC3200 and PC2700 (cont’d)
; V
DDQ
= 2.5 V ± 0.2 V,
Symbol –5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IS
LZ
MRD
QH
QHS
RAP
RAS
RC
RCD
REFI
RFC
RP
RPRE
RPST
RRD
WPRE
WPRES
WPST
WR
WTR
XSNR
XSRD
V
REF
V
V
REF
. CK/CK slew rate are ≥ 1.0 V/ns.
DD
stabilizes.
0.7
= +2.5 V ± 0.2 V (DDR333);
DDR400B
Min.
0.6
–0.7
2
t
t
40
55
15
65
15
0.9
0.40
10
0.25
0
0.40
15
2
75
200
HP
RCD
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
t
QH
16
Max.
+0.7
+0.50
70E+3 42
7.8
1.1
0.60
0.60
–6
DDR333
Min.
0.75
0.8
–0.7
2
t
t
60
18
72
18
0.9
0.40
12
0.25
0
0.40
15
1
75
200
Unbuffered DDR SDRAM Modules
HP
RCD
V
DDQ
t
QHS
= 2.6 V ± 0.1 V,
Max.
+0.7
+0.55
70E+3
7.8
1.1
0.60
0.60
Electrical Characteristics
09152006-1LHY-N6G4
V
DD
Rev. 1.11, 2007 - 01
Unit Note/ Test
ns
ns
ns
t
ns
ns
ns
ns
ns
ns
µs
ns
ns
t
t
ns
t
ns
t
ns
t
ns
t
CK
CK
CK
CK
CK
CK
CK
= +2.6 V ± 0.1 V
Condition
fast slew rate
3)4)5)6)8)
slow slew
rate
3)4)5)6)8)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
V
1)
TT
.

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