hys64t512622edl-2.5-a Qimonda, hys64t512622edl-2.5-a Datasheet - Page 4

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hys64t512622edl-2.5-a

Manufacturer Part Number
hys64t512622edl-2.5-a
Description
200-pin Dual-die So-dimm Modules With Thermal Sensor So-dimm Sdram
Manufacturer
Qimonda
Datasheet
1) This
2) Precharge-All command for an 8 bank device will equal to
1.2
The Qimonda HYS64T512622EDL–[2.5/25F/3S]–A module
family are Small-Outline DIMM modules “SO-DIMMs” with
Thermal Sensor and 30 mm height based on DDR2
technology. DIMMs are available as non-ECC modules in
512M × 64 (4GB) in organization and density, intended for
mounting into 200-pin connector sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400S–555–12–D0" where 6400S
Rev. 1.00, 2008-07
11052007-JHXM-ZQRH
Product Type
PC2-6400 (5-5-5)
HYS64T512622EDL-25F-A
PC2-6400 (6-6-6)
HYS64T512622EDL-2.5-A
PC2-5300 (5-5-5)
HYS64T512622EDL-3S-A
where
means Small-Outline DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "D".
t
PREA
t
nRP
value is the minimum value at which this chip will be functional.
= RU{
1)
t
RP
Description
/
t
CK(avg)
} and
Compliance Code
4GB 2R×8 PC2–6400S–555–12–D0
4GB 2R×8 PC2–6400S–666–12–D0
4GB 2R×8 PC2–5300S–555–12–D0
t
RP
is the value for a single bank precharge.
2)
t
RP
+ 1 ×
4
t
The memory array is designed with 4Gbit (2Gbit Dual-Dies)
Double-Data-Rate-Two
Decoupling capacitors are mounted on the PCB board. The
DIMMs feature serial presence detect based on a serial
E
128 bytes are programmed with configuration data and are
write protected; the second 128 bytes are available to the
customer.
CK
2
PROM device using the 2-pin I
or
t
nRP
+ 1 × nCK, depending on the speed bin,
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
Small Outline DDR2 SDRAM Modules
HYS64T512622EDL–[2.5/25F/3S]–A
(DDR2)
Ordering Information
SDRAM Technology
2Gbit (×8)
2Gbit (×8)
2Gbit (×8)
Synchronous
2
C protocol. The first
Internet Data Sheet
TABLE 2
DRAMs.

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