hys64t128020emv-2.5c2 Qimonda, hys64t128020emv-2.5c2 Datasheet - Page 19

• Manufacturer Part Number: hys64t128020emv-2.5c2
• Description: 214-pin 1.5v Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
• Manufacturer: Qimonda

29) 85 °C <
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
31)
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
35)
36) This timing parameter is relaxed than Industry Standard
1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
11) MIN (
12) The
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
14) 0 °C≤
15) 85 °C <
16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
17) The
18) The maximum limit for the
19) Minimum
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
21) WR must be programmed to fulfill the minimum requirement for the
Rev. 1.00, 2008-06
01242008-CDK4-KSK6
any Refresh command and the next Refresh command is 9 x
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
t
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
the WR parameter stored in the MR.
mis-match between DQS / DQS and associated DQ in any given cycle.
be greater than the minimum specification limits for
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
any Refresh command and the next Refresh command is 9 x
performance (bus turnaround) degrades accordingly.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
RPST
t
nRP
WTR
t
RPST
HZ,
DDQ
t
t
JIT.PER.MAX
JIT.DUTY.MAX
t
t
= RU{
t
t
t
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
HZ
RPST
RRD
end point and
t
), or begins driving (
= 1.8 V ± 0.1V;
CL
T
,
CASE
T
t
T
,
t
RPRE
RPST
), or begins driving (
timing parameter depends on the page size of the DRAM organization.
t
CASE
CASE
t
t
CH
WTR
RP
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
≤ 85 °C.
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
/
and
= 0.6 x
≤ 95 °C.
≤ 95 °C.
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
= + 93 ps, then
t
CK.AVG
= + 93 ps, then
t
LZ
t
t
RPRE
,
CK.AVG
t
V
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
t
CK.AVG
RPRE
DD
t
XARDS
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
RPRE
= 1.8 V ± 0.1 V.
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
t
t
DAL
t
LZ,
).
has to be satisfied.
RPRE.MIN(DERATED)
t
t
RPST.MIN(DERATED)
CK
Figure 2
parameter is not a device limit. The device operates with a greater value for this parameter, but system
t
= WR + (
RPRE
) independent of operation frequency.
).
V
t
HZ
REF
shows a method to calculate these points when the device is no longer driving (
t
RP
and
V
stabilizes. During the period before
/
TT
t
CK
=
.
t
=
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
t
RPRE.MIN
t
RPST.MIN
transitions occur in the same access time windows as valid data transitions.These
t
CL
and
+
+
t
t
t
t
XARD
JIT.PER.MIN
CH
JIT.DUTY.MIN
t
t
REFI
REFI
).
19
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
.
.
t
WR
= 0.9 x
timing parameter, where
= 0.4 x
Unbuffered DDR2 SDRAM MicroDIMM Modules
t
CK.AVG
t
CK.AVG
V
t
REF
CK
– 72 ps = + 2178 ps and
refers to the application clock period. WR refers to
– 72 ps = + 928 ps and
stabilizes, CKE = 0.2 x
t
nPARAM
HYS64T128020EMV–[2.5/3S](–)C2
WR
= RU{
MIN
t
t
JIT.PER
JIT.DUTY
t
t
[cycles] =
nRP
RP
t
PARAM
= 15 ns, the device will support
= RU{
of the input clock. (output
t
t
of the input clock. (output
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
V
/
t
DDQ
CK.AVG
Internet Data Sheet
t
t
RP
WR
is recognized as low.
t
/
t
(ns)/
JIT.DUTY.MIN
JIT.PER.MIN
t
}, which is in clock
CK.AVG
t
t
RPST
CK
}, which is in
(ns) rounded
), or begins
=
=
= – 72 ps
= – 72 ps
t
t
RPRE.MAX
RPST.MAX
t
CK