m470t5267az3 Samsung Semiconductor, Inc., m470t5267az3 Datasheet
m470t5267az3
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m470t5267az3 Summary of contents
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SODIMM DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 2Gb A-die 83DSP with Lead-Free and Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE ...
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... DDR2 Unbuffered DIMM Ordering Information ......................................................................... 4 2.0 Features ........................................................................................................................................ 4 3.0 Address Configuration ................................................................................................................ 4 4.0 Pin Configurations (Front side/Back side) ................................................................................ 5 5.0 Pin Description ............................................................................................................................ 5 6.0 Input/Output Function Description ............................................................................................ 6 7.0 Functional Block Diagram : 4GB, 512Mx64 Module - M470T5267AZ(H)3 ............................... 7 8.0 Absolute Maximum DC Ratings .................................................................................................. 8 9.0 AC & DC Operating Conditions .................................................................................................. 8 9.1 Recommended DC Operating Conditions (SSTL - 1.8) 9.2 Operating Temperature Condition ................................................................................................................... 9 9.3 Input DC Logic Level ...
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SODIMM Revision History Revision Month Year 1.0 December 2007 1.01 2007 December 1.1 July 2008 1.2 September 2008 - Initial Release - Typo Correction - Applied JEDEC update(JESD79-2E timing table - Erased the product of 800Mbps CL5 speed ...
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... Package: 83ball DSP - st.512Mx8 • All of base components are Lead-Free, Halogen-Free, and RoHS compliant Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. 3.0 Address Configuration Organization 256Mx8(2Gb) based Module Organiza- Density Component Composition tion ...
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... DQS2 Note : Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules. 5.0 Pin Description Pin Name Description CK0,CK1 Clock Inputs, positive line CK0,CK1 Clock Inputs, negative line CKE0,CKE1 Clock Enables RAS Row Address Strobe ...
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... DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are com- plements, and timing is relative to the crosspoint of respective DQS and DQS If the module oper- ated in single ended strobe mode, all DQS signals must be tied on the system board to V SDRAM mode registers programmed appropriately ...
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... SODIMM 7.0 Functional Block Diagram : 4GB, 512Mx64 Module - M470T5267AZ(H)3 (Populated as 2 ranks of x8 DDR2 SDRAMs) 3Ω CKE1 ODT1 S1 CKE0 ODT0 S0 DQS0 DQS DQS DQS0 DM DM0 DQ0 I/O 0 DQ1 I/O 1 DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS DQS DQS1 DM DM1 DQ8 I/O 8 DQ9 I/O 9 DQ10 I/O 10 DQ11 ...
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SODIMM 8.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on ...
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SODIMM 9.2 Operating Temperature Condition Symbol T Operating Temperature OPER Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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SODIMM 10.0 IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between ...
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... IDD3N 1,120 IDD4W 1,840 IDD4R 2,080 IDD5 2,720 IDD6 240 IDD7 3,280 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. e 667@CL=5 LF7 CE6 LE6 1,160 1,320 128 240 128 800 880 640 ...
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SODIMM 12.0 Input/Output Capacitance Parameter Non-ECC Input capacitance, CK and CK Input capacitance, CKE , CS, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS * DM is internally loaded to match DQ and DQS identically. 13.0 Electrical Characteristics ...
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SODIMM 13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK Average clock HIGH pulse ...
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SODIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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SODIMM 13.4 Timing parameters by speed grade (DDR2-533) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK HIGH pulse width CK LOW ...
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SODIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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... SODIMM 14.0 Physical Dimensions : st.512Mbx8 based 512Mx64 Module (2 Ranks) 1 11.40 16.25 2 DETAIL a FRONT SIDE 4.20 1.50 ± 0.10 2.70 ± 0.10 1.0 ± 0.05 4.00 ± 0.10 The used device is st.512M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T4G274QA - M470T5267AZ(H)3 67.60 mm 199 a b 47.40 63.00 200 a 67.60 mm BACK SIDE 4.00 ± 0.10 1.0 ± 0.05 1.80 ± 0.10 2.40 ± 0.10 4. DDR2 SDRAM Units : Millimeters 3 ...