m470t2953by3-ld5/cc Samsung Semiconductor, Inc., m470t2953by3-ld5/cc Datasheet - Page 14

• Manufacturer Part Number: m470t2953by3-ld5/cc
• Description: 200pin Unbuffered Sodimm Based On 512mb B-die 64bit Non-ecc
• Manufacturer: Samsung Semiconductor, Inc.

Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
256MB, 512MB, 1GB Unbuffered SODIMMs
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size products tRRD
Active to active command period for 2KB page size products tRRD
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command (Slow exit, Lower
power)
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
tIS
tRPRE
tRPST
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
Symbol
tHP - tQHS
tRFC + 10
2* tACmin
tWR+tRP
min(tCL,
WL-0.25
tAC min
6 - AL
3750
tCH)
0.45
0.45
0.35
0.35
37.5
min
-500
-450
225
100
0.35
375
250
200
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
10
50
15
x
2
2
2
x
x
2
DDR2-533
tAC max
WL+0.25
tAC max
tAC max
+500
+450
8000
max
0.55
0.55
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tHP - tQHS
tRFC + 10
2* tACmin
tWR+tRP
min(tCL,
WL-0.25
tAC min
6 - AL
5000
-600
-500
tCH)
0.45
0.45
0.35
0.35
0.35
37.5
min
275
150
0.35
475
350
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
15
10
x
2
2
2
2
x
x
DDR2-400
Rev. 1.5 Aug. 2005
WL+0.25
tAC max
tAC max
tAC max
DDR2 SDRAM
+600
+500
max
0.55
0.55
8000
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Notes