m470l6423ck0 Samsung Semiconductor, Inc., m470l6423ck0 Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
m470l6423ck0
Manufacturer Part Number
m470l6423ck0
Description
512mb Ddr Sdram Module 64mx64 Based On Ddp 64mx 8 Ddr Sdram 200pin Sodimm 64bit Non-ecc/parity
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M470L6423CK0.pdf
(14 pages)
DDR SDRAM module I
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
4. Timing patterns
* Module
M470L6423CK0
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD6
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
Symbol
IDD4W
IDD2P
IDD2Q
IDD3P
IDD3N
IDD4R
IDD7A
IDD2F
IDD0
IDD1
IDD5
I
DD
Low power
Normal
was calculated on the basis of component
typical
A2(DDR266@CL=2)
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
DD
spec table
worst
T.B.D
T.B.D
1216
1640
1520
1536
2760
896
432
280
616
48
48
B0(DDR266@CL=2.5)
typical
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
I
DD
and can be differently measured according to DQ loading cap.
worst
T.B.D
T.B.D
1216
1640
1520
1536
2760
896
432
280
616
48
48
200pin DDR SDRAM SODIMM
A0(DDR200@CL=2)
typical
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
worst
T.B.D
T.B.D
1144
1440
1320
1384
2280
824
368
264
544
48
48
Rev. 0.0 Aug. 2001
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Notes