m470l3224bto Samsung Semiconductor, Inc., m470l3224bto Datasheet - Page 9
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m470l3224bto
Manufacturer Part Number
m470l3224bto
Description
256mb Ddr Sdram Module
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M470L3224BTO.pdf
(14 pages)
Input/Output CAPACITANCE
AC OPERATING TEST CONDITIONS
M470L3224BT0
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input capacitance(A
Input capacitance(CKE
Input capacitance( CS
Input capacitance( CLK
Data & DQS input/output capacitance(DQ
Input capacitance(DM
IH
/V
IL
Parameter
)
0
Parameter
~ A
0
0
~DM
0
, CS
0
)
, CLK
11
, BA
1
8
)
)
1
Output
)
0
~ BA
(V
DD
1
,RAS,CAS, WE )
=2.5V, V
Output Load Circuit (SSTL_2)
0
~DQ
(V
Z0=50
DD
63
DDQ
)
=2.5V, V
C
LOAD
=2.5V, T
=30pF
V
tt
DDQ
=0.5*V
A
Symbol
= 25
C
=2.5V, T
V
C
C
C
C
C
OUT
REF
R
IN1
IN2
IN3
IN4
IN5
See Load Circuit
DDQ
T
=50
C
+0.31/V
0.5 * V
, f=1MHz)
200pin DDR SDRAM SODIMM
V
=0.5*V
Value
V
REF
A
1.5
V
= 0 to 70
REF
tt
DDQ
REF
DDQ
Min
-0.31
36
36
26
34
12
12
C
)
Rev. 0.1 June. 2001
Max
44
44
30
38
14
14
Unit
V
V
V
V
V
Unit
pF
pF
pF
pF
pF
pF
Note