k9f1g08r0a Samsung Semiconductor, Inc., k9f1g08r0a Datasheet - Page 31

• Manufacturer Part Number: k9f1g08r0a
• Description: 128m X 8 Bit / 256m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

R/B
K9F1G08R0A
K9F1G08U0A
Figure 9. Random Data Input In a Page
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program com-
mand (10h).
Figure 10. Cache Program
R/B
I/Ox
80h
Col Add1,2 & Row Add1,2
80h
Data Input*
Address &
Data
Col Add1,2 & Row Add1,2
K9K2G08U1A
Address & Data Input
15h
Data
t
CBSY
80h
Col Add1,2 & Row Add1,2
(available only within a block)
Data Input
Address &
Data
85h
15h
Address & Data Input
t
CBSY
Col Add1,2
80h
31
Data
Col Add1,2 & Row Add1,2
Data Input
Address &
Data
10h
15h
t
CBSY
t
PROG
80h
Col Add1,2 & Row Add1,2
FLASH MEMORY
Data Input
70h
Address &
Data
10h
I/O
Fail
t
0
PROG
"1"
"0"
70h
Pass