k4h1g0738b Samsung Semiconductor, Inc., k4h1g0738b Datasheet - Page 4

• Manufacturer Part Number: k4h1g0738b
• Description: Stacked 1gb B-die Ddr Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM stacked 1Gb B-die (x4/x8)
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H1G0638B-T(U)C/LA2
K4H1G0638B-T(U)C/LB0
K4H1G0738B-T(U)C/LA2
K4H1G0738B-T(U)C/LB0
Part No.
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
(Leaded & Pb-Free(RoHS compliant))
DQS
st.256M x 4
st.128M x 8
Org.
A2(DDR266@CL=2.0)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
133MHz
133MHz
2-3-3
package
Max Freq.
-
Interface
SSTL2
SSTL2
B0(DDR266@CL=2.5)
Rev. 1.5 June. 2005
100MHz
133MHz
2.5-3-3
DDR SDRAM
-
66pin TSOP II
66pin TSOP II
Package