ic42s16101-7tig ETC-unknow, ic42s16101-7tig Datasheet - Page 31

• Manufacturer Part Number: ic42s16101-7tig
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16101
Integrated Circuit Solution Inc.
DR025-0F 01/17/2005
Write Cycle Interruption Using the
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
CAS latency = 2, 3, burst length = 4
CAS latency = 2, 3, burst length = 4
Precharge Command
WDL
COMMAND
) from the precharge command to the point
COMMAND
CLK
I/O
DQM
CLK
I/O
WRITE (CA=A, BANK 0)
WRITE A0
D
WRITE (CA=A, BANK 0)
IN
A0
WRITE A0
D
IN
D
IN
A0
A1
D
IN
D
IN
A1
A2
D
IN
D
A2
IN
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write data
recovery period (t
precharge command must be executed on one clock cycle
that follows the input of the last burst data item.
t
A3
DPL
PRECHARGE (BANK 0)
CAS
CAS Latency
CAS
CAS
CAS
D
PRE 0
PRE 0
IN
A3
t
t
WDL
MASKED BY DQM
DPL
PRECHARGE (BANK 0)
t
WDL
=0
DPL
) has elapsed. Therefore, the
3
0
1
2
0
1
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