k4s510432m Samsung Semiconductor, Inc., k4s510432m Datasheet - Page 3

• Manufacturer Part Number: k4s510432m
• Description: 512mbit Sdram 4bit Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

K4S510432M
32M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
FUNCTIONAL BLOCK DIAGRAM
clock.
-. Burst length (1, 2, 4, 8 & Full page)
-. CAS latency (2 & 3)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
K4S510432M-TC/TL75
K4S510432M-TC/TL1H
K4S510432M-TC/TL1L
Latency & Burst Length
The K4S510432M is 536,870,912 bits synchronous high data
Programming Register
WE
Data Input Register
Column Decoder
32M x 4
32M x 4
32M x 4
32M x 4
Part No.
DQM
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.2 Dec. 2001
CMOS SDRAM
LDQM
Preliminary
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
54pin