k4s511632d-ul75 Samsung Semiconductor, Inc., k4s511632d-ul75 Datasheet - Page 4

• Manufacturer Part Number: k4s511632d-ul75
• Description: 512mb D-die Sdram
• Manufacturer: Samsung Semiconductor, Inc.

SDRAM 512Mb D-die (x4, x8, x16)
1.0 Features
2.0 General Description
3.0 Ordering Information
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
• 54pin TSOP II
•
33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
RoHS compliant
The K4S510432D / K4S510832D / K4S511632D is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8)
-. Burst type (Sequential & Interleave)
K4S510432D-UC(L)75
K4S510832D-UC(L)75
K4S511632D-UC(L)75
Part No.
Pb-Free
package
Organization
128Mx4
32Mx16
64Mx8
Row & Column address configuration
128Mb x 4 (CL=3)
32Mb x 16 (CL=3)
64Mb x 8 (CL=3)
Orgainization
Row Address
A0~A12
A0~A12
A0~A12
Max Freq.
133MHz
133MHz
133MHz
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
Rev. 1.0 November. 2005
Interface
LVTTL
CMOS SDRAM
54pin TSOP(II)
Package