k4s560832e-nl75 Samsung Semiconductor, Inc., k4s560832e-nl75 Datasheet
k4s560832e-nl75
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k4s560832e-nl75 Summary of contents
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 256Mb E-die SDRAM Specification * Samsung Electronics reserves the right to change products or specification without notice. 54pin sTSOP-II Revision 1.1 February. 2004 CMOS SDRAM Rev. 1.1 February, 2004 ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 Revision History Revision 1.0 (August. 2003) - First release. Revision 1.1 (February. 2004) - Deleted x16 for data book. CMOS SDRAM Rev. 1.1 February, 2004 ...
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... Cycle) GENERAL DESCRIPTION The K4S560432E / K4S560832E is 268,435,456 bits synchronous high data rate Dynamic RAM organized 16,777,216 words by 4bits / 4 x 8,388,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows pre- cise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, pro- grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 Package Physical Dimension 54pin sTSOP(II)-300 #54 (1.00) #1 14.40MAX (14.20) 14.00±0.10 (0.50) 0.50TYP 0.50±0.05 [ NOTE REFERENCE ASS’Y OUT QUALITY #28 (‡2.00 Dp0~0.05 BTM) #27 q (14 ) +0.075 0.20 -0.035 q ( 0.07 MAX CMOS SDRAM Units : Millimeters (2-R 0.30) (2-R 0.15) q (14 ) +0.075 ...
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... SDRAM 256Mb E-die (x4, x8 SDRAM 256Mb E-die (x4, x8) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE CS * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register 16M 16M ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 PIN CONFIGURATION (Top view VDD VDD DQ0 NC VDDQ VDDQ NC NC DQ1 DQ0 VSSQ VSSQ NC NC DQ2 NC VDDQ VDDQ NC NC DQ3 DQ1 VSSQ VSSQ NC NC VDD VDD CAS CAS RAS RAS ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... SDRAM 256Mb E-die (x4, x8 SDRAM 256Mb E-die (x4, x8) DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, T Parameter Symbol Burst length = 1 Operating current I t CC1 (One bank active CKE dV Precharge standby current in CC2 power-down mode I PS CKE & CLK dV CC2 CKE tV ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4 OPERATING TEST CONDITIONS Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200: Output 50pF 870: (Fig output load circuit ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4 CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4, x8 IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 I Characteristics (Pull-down) OL 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 0 ...
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... SDRAM 256Mb E-die (x4, x8) SDRAM 256Mb E-die (x4 Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 CMOS SDRAM Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...