k4h560838j Samsung Semiconductor, Inc., k4h560838j Datasheet - Page 19

• Manufacturer Part Number: k4h560838j
• Description: 256mb J-die Ddr Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
21. tQH = tHP - tQHS, where:
22. tDQSQ
23. tDAL = (tWR/tCK) + (tRP/tCK)
K4H560438J
K4H560838J
K4H561638J
device design or tester correlation.
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
19 of 24
Rev. 1.0 September 2007
DDR SDRAM