k4h510438 Samsung Semiconductor, Inc., k4h510438 Datasheet - Page 3

• Manufacturer Part Number: k4h510438
• Description: Ddr Sdram 512mb B-die X4, X8, X16
• Manufacturer: Samsung Semiconductor, Inc.

DDR SDRAM 512Mb B-die (x4, x8, x16)
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
Operating Frequencies
*CL : CAS Latency
Ordering Information
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H510438B-TC/LB3
K4H510438B-TC/LA2
K4H510438B-TC/LB0
K4H510838B-TC/LB3
K4H510838B-TC/LA2
K4H510838B-TC/LB0
K4H511638B-TC/LB3
K4H511638B-TC/LA2
K4H511638B-TC/LB0
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Part No.
128M x 4
32M x 16
64M x 8
Org.
B3(DDR333@CL=2.5)
133MHz
166MHz
2.5-3-3
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Max Freq.
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
Interface
SSTL2
SSTL2
SSTL2
Rev. 1.2 October, 2004
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
66pin TSOP II
66pin TSOP II
66pin TSOP II
2.5-3-3
Package