k4s161622h Samsung Semiconductor, Inc., k4s161622h Datasheet - Page 10

• Manufacturer Part Number: k4s161622h
• Description: 16mb H-die Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

(AC operating conditions unless otherwise noted)
SDRAM 16Mb H-die(x16)
Notes :
CLK cycle time
CLK to valid
output delay
Output data
CLK high pulse
width
CLK low pulse
width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Parameters depend on programmed CAS latency.
6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
7. Assumed input rise and fall time (tr & tf)=1ns.
8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
Symbol
t
t
t
t
t
t
t
SAC
t
t
SHZ
SLZ
CC
OH
CH
SH
CL
SS
Min
5.5
1.5
10
2
2
3
2
3
2
1
1
-
-
-
-
55
1000
Max
5
6
5
6
-
-
-
-
-
-
Min
2.5
2.5
2.5
1.5
10
6
3
3
2
1
1
-
-
-
-
60
1000
Max
5.5
5.5
6
6
-
-
-
-
-
-
1.75
Min
2.5
10
7
3
3
2
1
1
-
-
-
-
-70
1000
Max
5.5
5.5
6
6
-
-
-
-
-
-
Rev. 1.5 August 2004
Min
2.5
10
8
3
3
2
1
1
-
-
-
CMOS SDRAM
-
-80
1000
Max
6
6
6
6
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
5, 6
5
6
7
7
7
7
6