k4t51043qb-zcd5 Samsung Semiconductor, Inc., k4t51043qb-zcd5 Datasheet - Page 27

• Manufacturer Part Number: k4t51043qb-zcd5
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

31. Input waveform timing is referenced from the input signal crossing at the V
device under test.
32. Input waveform timing is referenced from the input signal crossing at the V
device under test.
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the sin-
gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-
ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the sin-
gle-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-
ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic
between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of tIS
+ 2*tCK + tIH.
512Mb B-die DDR2 SDRAM
CK
CK
tIS
tIH
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IH(ac)
IH(dc)
tIS
level for a rising signal and V
level for a rising signal and V
tIH
IL(ac)
IL(dc)
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
for a falling signal applied to the
for a falling signal applied to the
max
max
min
min
DDR2 SDRAM
Rev. 1.5 July 2005