am42bds6408g Meet Spansion Inc., am42bds6408g Datasheet - Page 85

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am42bds6408g

Manufacturer Part Number
am42bds6408g
Description
64 Mbit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 8 Mbit 512 K ? 16-bit Static Ram Preliminary
Manufacturer
Meet Spansion Inc.
Datasheet
SRAM AC CHARACTERISTICS
Notes:
1. CE1#s controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
October 23, 2003
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
Figure 50. SRAM Write Cycle—CE1#s Control
A D V A N C E
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
t
AS
(See Note 2 )
Am42BDS6408H
I N F O R M A T I O N
(See Note 3)
WR
t
t
AW
applied in case a write ends as CE1#s or WE# going high.
CW
t
(See Note 5)
WC
t
BW
t
WP
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
(See Note 4)
High-Z
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