am42dl6404g Meet Spansion Inc., am42dl6404g Datasheet - Page 57

• Manufacturer Part Number: am42dl6404g
• Description: 64 Mbit 8 M ? 8-bit/4 M ? 16-bit Cmos And 4 Mbit 256 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

SRAM AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
3. t
4. t
5. A write occurs during the overlap (t
6. Output data may be present on the bus at this time; input signals should not be applied.
7. If OE# is high during the write cycle, the outputs will remain at high impedance.
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when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
CE1#s
CE2s
Address
UB#s, LB#s
WE#
Data In
Data Out
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
High-Z
(See Note 4)
P R E L I M I N A R Y
t
AS
Am42DL6404G
WR
(See Note 2)
t
applied in case a write ends as CE1#s or WE# going high.
CW
t
t
AW
WC
(See Note 5)
t
t
CW
(See Note 2)
BW
t
WP
t
DW
Data Valid
WP
t
WR
is measured from the beginning of write
t
DH
(See Note 3)
High-Z
March 20, 2002