am41pds3228d Meet Spansion Inc., am41pds3228d Datasheet - Page 25

• Manufacturer Part Number: am41pds3228d
• Description: 32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 8 Mbit 1 M ? 8-bit/512 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
V
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at V
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
24
HH
Increment
Address
on the WP#/ACC pin, the device automatically en-
Figure 3. Unlock Bypass Algorithm
Program Address/Program Data
Programming Completed
No
Data# Polling Device
(BA) XXXh/90h
Last Address
Verify Byte?
XXXh/A0h
XXXh/00h
555h/AAh
2AAh/55h
555h/20h
Start
?
Yes
Yes
No
HH
any operation
P R E L I M I N A R Y
In
Unlock
Bypass
Program
Set
Unlock
Bypass
Mode
Reset
Unlock
Bypass
Mode
Am41PDS3228D
Figure 4 illustrates the algorithm for the program oper-
ation. Refer to the Flash Erase and Program Opera-
tions table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
Note: See Table 10 for program command sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
Increment Address
Figure 4. Program Operation
Embedded
in progress
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
May 13, 2002
No