am41pds3224d Meet Spansion Inc., am41pds3224d Datasheet - Page 14

• Manufacturer Part Number: am41pds3224d
• Description: 32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 4 Mbit 512 K ? 8-bit/256 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
eration.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
l e c t C o m m a n d S e q u e n c e s e c t i o n s f o r m o r e
information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
with in the same bank (e xce pt the sector being
erased). Figure 21 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. I
t a b le re p r e se n t t h e cu r re n t s p e cif ic a t io n s fo r
r e a d - w h i l e - p r o g r a m a n d r e a d - w h i l e - e r a s e ,
respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The de-
vice requires standard access time (t
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
May 13, 2002
CC3
HH
IH
.) If CE#f and RESET# are held at V
from the ACC pin returns the device to normal op-
in the Flash DC Characteristics table represents
CC
CC6
± 0.3 V, the device will be in the standby
and I
CC7
in the Flash DC Characteristics
CE
P R E L I M I N A R Y
CC
IH
) for read
, but not
± 0.3 V.
Am41PDS3224D
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Automatic sleep mode current is drawn when CE# =
V
CE# and RESET# voltages are not held within these
tolerances, the automatic sleep mode current will be
greater.
I
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
vice draws CMOS standby current (I
is held at V
current will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus mon itor RY/BY# to de term ine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
CC5
SS
f in the Flash DC Characteristics table represents
± 0.3 V and all inputs are held at V
READY
IL
but not within V
(during Embedded Algorithms). The
READY
IH
.
IH
, output from the device is
SS
(not during Embedded
± 0.3 V, the standby
SS
CC3
± 0.3 V, the de-
f). If RESET#
CC
RH
± 0.3 V. If
after the
RP
ACC
, the
13
+