uss820d-db ETC-unknow, uss820d-db Datasheet - Page 31

• Manufacturer Part Number: uss820d-db
• Description: Uss-820d Device Controller
• Manufacturer: ETC-unknow

June 2001
Agere Systems Inc.
Register Interface
Table 27. Receive FIFO Byte-Count High and Low Registers (RXCNTH, RXCNTL)—Address: RXCNTH =
High and low registers are in a two-register ring buffer that is used to store the byte count for the data packets
received in the receive FIFO specified by EPINDEX. These registers are endpoint indexed.
Table 28. Receive FIFO Control Register (RXCON)—Address: 08H; Default: 0000 0100B
Controls the receive FIFO specified by EPINDEX. This register is endpoint indexed.
* Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes.
15:10
Bit
9:0
Bit
6:5
RXCLR
Bit 15
7
Bit 7
Bit 7
BC7
07H, RXCNTL = 06H; Default: RXCNTH = 0000 0000B, RXCNTL = 0000 0000B
FFSZ[1:0] FIFO Size. These bits select the size of the receive FIFO.
Symbol
RXCLR
Symbol
BC[9:0]
—
FFSZ1
Bit 14
Bit 6
Bit 6
BC6
Receive FIFO Clear. Setting this bit flushes the receive FIFO, resets all the read/write
pointers and markers, resets the RXSETUP, STOVW, EDOVW, RXVOID, RXERR, and
RXACK bits of the RXSTAT register, sets the RXEMP bit in RXFLG register, and clears all
other bits in RXFLG register. Hardware clears this bit when the flush operation is
completed. Setting this bit does not affect the RXSEQ bit of RXSTAT. This bit should only
be set when the endpoint is disabled or there is a FIFO error present. Firmware should
never set this bit to clear a SETUP packet. The next SETUP packet will automatically clear
the receive FIFO.
FFSZ[1:0]
Reserved. Write 0s to these bits. Reads always return 0s.
Receive Byte Count (Read Only). 10-bit, ring buffer byte. Stores receive byte count
(RXCNT).
(continued)
00
01
10
11
FFSZ0
Bit 13
Bit 5
Bit 5
BC5
Nonisochronous Size Isochronous Size
—
—
RXFFRC
Bit 12
Bit 4
Bit 4
BC4
32*
16
64
8*
R/W
R
Function/Description
Function/Description
RXISO
Bit 11
Bit 3
Bit 3
BC3
1024
256
512
64
Bit 10
Bit 2
Bit 2
ARM
BC2
USB Device Controller
ADVWM
Bit 9
Bit 1
Bit 1
BC9
BC1
R
REVWP
Bit 8
Bit 0
Bit 0
BC8
BC0
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