plrxpl-vc-sh4-21-n ETC-unknow, plrxpl-vc-sh4-21-n Datasheet - Page 2

• Manufacturer Part Number: plrxpl-vc-sh4-21-n
• Description: Limiting Transceiver
• Manufacturer: ETC-unknow

2
Section 1
The PLRXPL-VC-SH4-xx-N 8.5 G SFP+ 850 nm optical transceiver is designed to
transmit and receive 8B/10B scrambled 8.5 G serial optical data over 50/125 µm or
62.5/125 µm multimode optical fiber.
Transmitter
The transmitter converts 8B/10B scrambled serial PECL or CML electrical data into
serial optical data compliant with the 8 G Fibre Channel standard. Transmit data
lines (TD+ and TD-) are internally AC coupled, with 100 Ω differential termination.
Transmitter rate select (RS1) pin 9 is assigned to control the SFP+ module trans-
mitter rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal
on this pin does not affect the operation of the transmitter.
An open collector-compatible transmit disable (Tx_Disable) is provided. This pin
is internally terminated with a 10 kΩ resistor to V
tion, on this pin will disable the laser from transmitting. A logic “0” on this pin
provides normal operation.
The transmitter has an internal PIN monitor diode that ensures constant optical
power output, independent of supply voltage. It is also used to control the laser
output power over temperature to ensure reliability at high temperatures.
An open collector-compatible transmit fault (Tx_Fault) is provided. The Tx_
Fault signal must be pulled high on the host board for proper operation. A logic
“1” output from this pin indicates that a transmitter fault has occurred or that
the part is not fully seated and the transmitter is disabled. A logic “0” on this pin
indicates normal operation.
Receiver
The receiver converts 8B/10B scrambled serial optical data into serial PECL/CML
electrical data. Receive data lines (RD+ and RD-) are internally AC coupled with
100 Ω differential source impedance, and must be terminated with a 100 Ω dif-
ferential load.
Receiver Rate Select (RS0) pin 7 is assigned to control the SFP+ module receiver
rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal on this
pin has no affect on the operation of the receiver.
An open collector compatible loss of signal (LOS) is provided. The LOS must be
pulled high on the host board for proper operation. A logic “0” indicates that light
has been detected at the input to the receiver (see Optical Characteristics, Loss of
Signal Assert/Deassert Time). A logic “1” output indicates that insufficient light
has been detected for proper operation.
8.5 G SFP+ 850 NM LIMITING TRANSCEIVER,
8 GIGABIT FIBRE CHANNEL COMPLIANT
Functional Description
cc,T
. A logic “1,” or no connec-