co561ad-d Connect One Ltd., co561ad-d Datasheet - Page 18

• Manufacturer Part Number: co561ad-d
• Description: The Co561ad-d Ichip Plus? Internet Controller? Is A Low-cost Intelligent Peripheral Device That Provides Internet Connectivity Solutions To A Myriad Of Embedded Devices.
• Manufacturer: Connect One Ltd.

Signal
-BHE
-UCS
-LCS
HOLD
HLDA
-RD
-WR
iChip CO561AD-D Datasheet
Type
O
O
O
O
O
O
I
Pin No.
31
14
21
62
61
68
52
BUS HIGH Enable: This pin and the least-significant
address bit (AD0 or A0) indicate to the system which
bytes of the data BUS (upper, lower, or both) participate
in a BUS cycle. The -BHE and A0 pins are encoded as
shown in the table below.
During a BUS hold or reset condition, -BHE is in a
HIGH impedance state.
This pin should be Connected to -BHE of LAN
controller if it exists.
Upper Chip Select: When –UCS is LOW, iChip Plus
accesses internal flash memory.
This pin should be left Not Connected.
Lower Chip Select: When –LCS is LOW, iChip Plus
accesses internal SRAM memory.
This pin should be left Not Connected.
BUS Hold Request: when HOLD is HIGH, it indicates
that an external BUS master needs control of the local
BUS.
This pin should be connect to GND.
BUS Hold Acknowledge: This pin goes HIGH to
indicate to an external BUS master that iChip Plus has
released control of the local BUS.
This pin should be left Not Connected.
READ: This pin indicates that iChip Plus is performing
a memory read cycle. -RD floats during a BUS hold
condition.
This pin should be Connected to -RD of the LAN
controller.
WRITE: This pin indicates that iChip Plus is
performing a memory write cycle. -WR floats during a
BUS hold condition.
This pin should be Connected to the LAN controller’s -
WR signal.
-BHE
0
1
0
1
AD0
0
0
1
1
Type of BUS cycle
Word Transfer
Even Byte Transfer
Odd Byte Transfer
N/A
Description
Pin Descriptions
5-3