co561ad-l Connect One Ltd., co561ad-l Datasheet - Page 17

• Manufacturer Part Number: co561ad-l
• Description: The Co561ad-l Ichip Lan? Internet Controller? Is Part Of A Family Of Intelligent Peripheral Devices That Provides Internet Connectivity Solutions To A Myriad Of Embedded Devices.
• Manufacturer: Connect One Ltd.

11-3700-00
-BHE
HOLD
HLDA
-RD
-WR
iChip CO561AD-L Datasheet
Signal
Type
O
O
O
O
I
Pin No.
31
62
61
68
52
BUS HIGH Enable: This pin and the least-significant
address bit (AD0 or A0) indicate to the system, which
bytes of the data BUS (upper, lower, or both) participate
in a BUS cycle. The ~BHE and A0 pins are encoded as
shown in the table below.
During a BUS hold or reset condition, -BHE is in a
HIGH-impedance state.
This pin should be connected to -BHE of the LAN
controller.
BUS Hold Request: when HOLD is HIGH, it indicates
that an external BUS master needs control of the local
BUS.
This pin should be connected to GND.
BUS Hold Acknowledge: This pin goes HIGH to
indicate to an external BUS master that the iChip LAN
has released control of the local BUS.
This pin should be left Not Connected.
READ: This pin indicates that the iChip LAN is
performing a memory read cycle. -RD floats during a
BUS hold condition.
This pin should be connected to -RD of the LAN
controller.
WRITE: This pin indicates that the iChip LAN is
performing a memory write cycle. -WR floats during a
BUS hold condition.
This pin should be connected to -WR of the LAN
controller.
-BHE
0
1
0
1
AD0
0
0
1
1
Type of BUS cycle
Word Transfer
Even Byte Transfer
Odd Byte Transfer
N/A
Description
Pin Descriptions
5-3