bcm5682 Broadcom Corp., bcm5682 Datasheet - Page 2

• Manufacturer Part Number: bcm5682
• Description: Bcm5682 8-port Gigabit Switch On A Chip
• Manufacturer: Broadcom Corp.

The BCM5682 represents the highest level of cost-reduction and
integration available for the Gigabit Ethernet market. A Broadcom-based
eight-port Gigabit switch reduces today’s costs by as much as 50% over
competing solutions.
The I2C interface supports both master and slave modes of operation.
This interface is designed to support the unmanaged and Smart Switch
market, achieving the lowest possible system cost and the highest level
of design efficiency and reliability.
The 10/100/1000 Mbit interface enables users to connect at any speed
required on a given port. This triple-speed interface automatically
negotiates to support legacy devices alongside newer, higher bandwidth
devices, all in the same switch.
The PHY interface is compatible with a BCM8002 SERDES for fiber
optics, a BCM5401, BCM5402, BCM5404, or BCM5411 Gigabit PHY
for 1000TX, or a standard 100TX PHY.
The integrated 512 KB data packet memory eliminates the need for
external data packet storage. The memory organization and structure can
be optimized to provide a minimum fixed allocation of buffer space per
port and a dynamic pool size, to absorb any bursty traffic requirements.
Broadcom
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
5682-PB05-R
®
, the pulse logo, and Connecting everything
Micr oc on tr oller
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07/08/04
Seri al Bus
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are trademarks of Broadcom Corporation and/
PACKET BUFFER
NON-BL OCKING
SWITCH FABRIC
4 CoS QUEUES
I
Int erface
2
ARL TA BLES
C-Compatible
512 KB
BCM5682
O V E R V I E W
The BCM5682 supports IEEE 802.1p with up to four Class of Service
(CoS) queues per egress port, along with traffic class expediting and
dynamic multicast filtering.
The chip implements a number of advanced mechanisms for flow
control. Two mechanisms, cell-based HOL blocking and packet-based
HOL blocking, to prevent Head Of Line blocking on a per-port basis.
A packet aging mechanism discards packets residing in the switch’s
packet memory. The packet age limit is programmable.
A backpressure mechanism allows flexible flow control on packet
transactions. The limit at which backpressure is detected is based on the
amount of memory utilized by the packets on an input port. This limit is
programmable on a per-port basis.
Another mechanism provides programmable threshold limits to prevent
packets from flooding into other parts of the network. Three types of
packets can be monitored and separate counters are maintained from
each type of packet.
In summary, the highly flexible BCM5682 provides 12 Mpps (line rate)
switching along with sophisticated packet flow and prioritization
capabilities.
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 GMAC
10/100/1000 MBIT CAPABL E
EIGHT GIGABIT PORTS
(GMII OR 8B/10B)
Phone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web: www.broadcom.com