ocx1601 ETC-unknow, ocx1601 Datasheet - Page 36

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ocx1601

Manufacturer Part Number
ocx1601
Description
Ocx1601 Crosspoint Switch
Manufacturer
ETC-unknow
Datasheet
8. Component Availability and Ordering Information
9. Glossary
OCX1601 Crosspoint Switch—Advanced Datasheet
36
CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave
configuration to provide an update for programming and changing program information all at once.
CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port.
INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with
selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on
either side of the IO Buffer.
PORT: A name followed by a number to identify a pin on the device.
RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 23 dedicated
pins to program the Crosspoint Array and the IO Buffers. The 23 pins consist of an enable, a clock, four
instruction bits, two seven-bit address fields, and a three-bit data field.
Family
# I/O Ports
Speed Grade
Package Code
Temperature Range
Blank = 667 Mb/s
1 = 1.6 Gb/s
PB420 = Ball Grid Array
Blank - Commercial (0°C to 70°C)
I - Industrial (-40°C to +85°C)
[Rev. 1.8] 3/21/02
OCXxxxs - PP###T
Fairchild Semiconductor

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