njg1647hd3 New Japan Radio Co.,Ltd, njg1647hd3 Datasheet - Page 4

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njg1647hd3

Manufacturer Part Number
njg1647hd3
Description
Spdt Switch Gaas Mmic
Manufacturer
New Japan Radio Co.,Ltd
Datasheet
! TERMINAL INFORMATION
- 4 -
GND
No.
1
2
3
4
5
6
SYMBOL
CTL2
CTL1
GND
VDD
PC
P1
P2
Common RF port. This PC port is connected to P1 or P2 by logical
control voltage of CTL1.
In order to block DC bias voltage of internal circuit, an external capacitor
is required.
Control port 2. This terminal is set to +1.3~5.0V of logical high level as
usual, and set to +0.0~0.4V of logical low level for the low current
consumption mode.
Supply voltage terminal (+2.5~3.6V). Please place an inductor close to
this terminal, and a bypass capacitor between VDD and GND for
avoiding RF characteristic degradation.
Control port 1. This terminal is set to +1.3~5.0V of logical high level for
ON state between PC and P1 ports, and set to +0.0~0.4V of logical low
level for ON state between PC and P2 RF ports.
This port is connected with PC port by control voltage of
+1.3~5.0V(V
the DC bias voltage of internal circuit.
This port is connected to PC port by control voltage of +0.0~0.4V(V
to 4th pin. An external capacitor is required to block the DC bias voltage
of internal circuit.
Ground terminal. Please connect this terminal with ground plane as close
as possible for good RF performance.
CTL(H)
) to 4th pin. An external capacitor is required to block
DESCRIPTION
NJG1647HD3
CTL(L)
)

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