njg1723kt2 New Japan Radio Co.,Ltd, njg1723kt2 Datasheet - Page 5

• Manufacturer Part Number: njg1723kt2
• Description: Njg1723kt2 Phs Transceiver Gaas Mmic
• Manufacturer: New Japan Radio Co.,Ltd

TERMINAL INFORMATION
No.
10
11
12
13
1
2
3
4
5
6
7
8
9
NC(GND)
SYMBOL
LNAOUT
LNACAP
IFOUT
LNAIN
MIXIN
GND1
GND2
VBB3
LOIN
BPC
VLO
P2
This terminal is for base bias supply of the 3rd stage of power amplifier.
Operation current of the power amplifier is adjusted by changing the bias
voltage applied to this terminal. Please connect bypass capacitors C13 and C14
with ground plane close to this terminal. Please connect pin 23 and pin 24, and
connect the resistor R1 for temperature characteristic compensation of PA gain.
IF signal output terminal. The IF signal is output through external matching
circuit connected to this terminal. Please connect inductances L7, L8 and power
supply as shown in the application circuit, since this terminal is also the terminal
of mixer power supply.
Power supply terminal for local amplifier. Please place L6 and C9 shown in the
application circuit, very close to this terminal.
Local signal input terminal connected to the local amplifier. An external
matching circuit is required.
Terminal to connect to the external bypass capacitor of mixer. The bypass
capacitor C8 shown in the application circuit should be connected to this
terminal as close as possible.
Input terminal of RF signal to the mixer. An external matching circuit is required.
Ground terminal (0V)
Output terminal of LNA. The RF signal from LNA goes out through external
matching circuit connected to this terminal. Please connect inductances L4, L5
and power supply as shown in the application circuit, since this terminal is also
the terminal of LNA power supply.
Terminal to connect to an external bypass capacitor of LNA. The bypass
capacitor C5 shown in the application circuit should be connected to this
terminal as close as possible.
RF input terminal of LNA. An external matching circuit is required.
Ground terminal (0V)
RF port. This terminal is one of ports of SPDT SW. This terminal connects to
PC terminal (pin 15) when logical high voltage signal is supplied to VCTL2 (pin
14) and logical low voltage signal is supplied to VCTL1 (pin 16). External
capacitor C3 is required to block the DC bias voltage of internal circuit.
Nonconnection terminal. Please connect with Ground terminal.
DESCRIPTION
NJG1723KT2
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