sky65152 Skyworks Solutions, Inc., sky65152 Datasheet - Page 5

• Manufacturer Part Number: sky65152
• Description: 2.4-2.5 Ghz Wlan Power Amplifier
• Manufacturer: Skyworks Solutions, Inc.

Theory of Operation
The SKY65152 is a three-stage, HBT InGaP device optimized for
high linearity and power efficiency. It contains all of the needed
RF matching and DC biasing circuits. An in-module active bias
circuit is included within the device for all three amplifier stages
providing for excellent gain tracking over temperature and
voltage variations. The first, second and output stages are inde-
pendently supplied using the V
pins 16, 14 and 11,respectively. The DC control voltage that
sets the bias for all 3 stages is supplied via V
evaluation board includes shunt decoupling caps on these pins to
suppress any possible bias affect on the RF at low frequencies.
The bias reference voltages for stages 1, 2 and 3 are supplied
using common lines V
maximum reference voltage at the package pins is 4 V. Resistors
R1, R2 and R3 on the evaluation board set the correct bias to
these pins when attached to a 5 V power supply.
The SKY65152 includes an internal PA Enable control pin (Pin
3) for fast RF On/Off control of < 0.5 µs. Zero volts turns off the
PA while 3–5 V will turn on the PA. The device also provides an
output power detector voltage V
required to operate the detector. The detector supply voltage
is supplied via V
package pin is 4 V. Resistor R5 on the evaluation board sets the
correct bias to this pin when attached to a 5 V power supply.
Pin 18 is the RF input and Pin 9 is the RF output. External DC
blocking or RF matching is not required on the RF input and
output. Ground is achieved through several ground pins and the
package backside, center ground.
These features make the device suitable for wideband digital
applications, where PA linearity and power consumption are of
critical importance (e.g., WLANs). The device has been character-
ized with the highest specified data rates for 802.11b (11 Mbps)
and 802.11g (54 Mbps). Under these stringent test conditions,
the device exhibits excellent spectral purity and power efficiency.
Application Circuit Notes
Center Ground. It is extremely important that the device paddle
be sufficiently grounded for both thermal and stability reasons.
Multiple small vias are acceptable and will work well under the
device if solder migration is an issue.
Ground (pins 1, 2, 8, 10, 17, 19, 20). Attach all ground pins to
the RF ground plane with the largest diameter and lowest induc-
tance via that the layout will allow. Multiple small vias are also
acceptable and will work well under the device if solder migra-
tion is an issue.
CC_DET
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
200968 Rev. C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice. • April 7, 2009
REF1
(Pin 15). The maximum voltage at the
, V
REF2
CC1
DET
and V
, V
at Pin 14. A bias voltage is
CC2
REF3
and V
(Pins 5, 6 and 7). The
C_BIAS
CC3
supply lines,
, pin 4. The
pa_enB (pin 3). PA_ENB is the internal PA Enable control pin
for fast RF On/Off control of < 0.5 µs. Zero volts turns off the PA
while 3–5 V will turn on the PA.
V
and 2, typically set to 5 V.
V
should be operated over the same voltage range as V
nominal voltage of 5 V.
V
should be operated over the same voltage range as V
nominal voltage of 5 V.
V
should be operated over the same voltage range as V
nominal voltage of 5 V.
rF_OUt (pin 9). Amplifier RF Output Pin. Z
module includes an onboard internal DC blocking capacitor. All
impedance matching is provided internal to the module.
V
bias (typically 5 V). bypassing of V
and C17 and should be placed in the approximate location shown
on the evaluation board, but placement is not critical.
no Connect (pin 12). The pin is open and may or may not be
connected to ground.
V
(typically 5 V). Bypassing of V
C16 and should be placed in the approximate location shown on
the evaluation board, but placement is not critical.
V
load and settling time constant are set external to the device.
Inductor L2 and capacitor C7 are set to yield a settling time of
less than 0.5 µs.
V
and bypassing is V
capacitor C5 provided. V
supply. The benefit of doing this is the current draw consumed
by the detector will not be wasted with the PA in the “Off” state.
V
(typically 5 V). Bypassing of V
C15 and should be placed in the approximate location shown on
the evaluation board, but placement is not critical.
rF_in (pin 18). Amplifier RF Input Pin. Z
includes an onboard internal DC blocking capacitor. All imped-
ance matching is provided internal to the module.
C_Bias
reF1
reF2
reF3
CC3
CC2
det
CC_det
CC1
(pin 11). Supply voltage for the output (final) stage collector
(pin 13). Supply voltage for the second stage collector bias
(pin 14). Output power detector voltage pin. The detector
(pin 16). Supply voltage for the first stage collector bias
(pin 5). Bias reference voltage for amplifier stage 1. V
(pin 6). Bias reference voltage for amplifier stage 2. V
(pin 7). Bias reference voltage for amplifier stage 3. V
(pin 4). V
(pin 15). Power detector supply voltage. Proper bias
C_BIAS
CC_DET
CC_DET
is the bias supply voltage for stages 1
is accomplished with Resistor R5 and
preliminary Data Sheet • SKy65152
CC2
CC1
may be connected to PA_ENB
is accomplished with C8 and
is accomplished with C5 and
CC3
is accomplished with C10
O
= 50 W. The module
O
= 50 W. The
CC
CC
CC
, with a
, with a
, with a
REF1
REF2
REF3
5