s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 24

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

A d v a n c e
I n f o r m a t i o n
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Op-
erations table for timing specifications and to Figure 11 for the timing diagram.
Refer to the DC Characteristics table for the active current specification on read-
ing array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. The page size of the device is 8 words/16 bytes.
The appropriate page is selected by the higher address bits A(max)–A3. Address
bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word
within a page. This is an asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t
or t
and subsequent page
ACC
CE
read accesses (as long as the locations specified by the microprocessor falls
within that page) is equivalent to t
. When CE# is de-asserted and reasserted
PACC
for a subsequent access, the access time is t
or t
. Fast page mode accesses
ACC
CE
are obtained by keeping the “read-page addresses” constant and changing the
“intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to V
, and OE# to V
.
IL
IH
The device features an Unlock Bypass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The “Word/Byte Program
Command Sequence” section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 2 indicates the address space that each sector occupies.
Refer to the DC Characteristics table for the active current specification for the
write mode. The AC Characteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32
bytes in one programming operation. This results in faster effective programming
time than the standard programming algorithms. See “Write Buffer” for more
information.
24
S29GLxxxN MirrorBit
Flash Family
TM
S29GLxxxN_00_A4 June 14, 2004