9db233 Integrated Device Technology, 9db233 Datasheet - Page 4

• Manufacturer Part Number: 9db233
• Description: Two Output Differential Buffer For Pcie Gen3
• Manufacturer: Integrated Device Technology

IDT
1
2
TA = T
1
2
3
4
5
Electrical Characteristics - Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Parameters
SMBus Output Low Voltage
3.3V Logic Supply Voltage
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are >200 mV
DIF_IN input
The differential input clock must be running for the SMBus to be active
3.3V Core Supply Voltage
SMBus Input High Voltage
Operation under these conditions is neither implied nor guaranteed.
SMBus Input Low Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
9DB233
Two Output Differential Buffer for PCIe Gen3
®
Junction Temperature
Nominal Bus Voltage
Storage Temperature
Input ESD protection
SMBus Sink Current
Input SS Modulation
Ambient Operating
Input High Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
SMBus Operating
Two Output Differential Buffer for PCIe Gen3
Input Frequency
Clk Stabilization
Pin Inductance
COM
PARAMETER
PARAMETER
Input Current
OE# Latency
Temperature
Capacitance
Tdrive_PD#
Frequency
Frequency
or T
Trise
Tfall
IND;
Supply Voltage VDD = 3.3 V +/-5%
SYMBOL
SYMBOL
C
ESD prot
f
t
V
V
V
I
t
V
f
MAXSMB
T
LATOE#
V
INDIF_IN
PULLUP
t
VDDA
T
C
DRVPD
t
F
MODIN
T
VDD
OLSMB
DDSMB
RSMB
V
I
F
L
C
IHSMB
FSMB
V
ILSMB
I
STAB
IHSMB
COM
INP
t
V
V
ibyp
OUT
t
Ts
IND
IN
pin
Tj
ipll
R
IH
IN
F
IL
IL
IH
V
stabilization or de-assertion of PD# to 1st clock
IN
V
Single-ended inputs, V
IN
= VDD; Inputs with internal pull-down resistors
From V
Single-ended inputs, except SMBus, low
Single-ended inputs, except SMBus, low
= 0 V; Inputs with internal pull-up resistors
Maximum SMBus operating frequency
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
V
DIF stop after OE# deassertion
DIF_IN differential clock inputs
DD
DIF start after OE# assertion
threshold and tri-level inputs
threshold and tri-level inputs
Logic Inputs, except DIF_IN
V
Rise time of control inputs
DD
Except for SMBus interface
SMBus clock and data pins
Fall time of control inputs
= 3.3 V, 100MHz PLL mode
DD
Output pin capacitance
(Triangular Modulation)
DIF output enable after
Allowable Frequency
Power-Up and after input clock
Commmercial range
Single-ended inputs
= 3.3 V, Bypass mode
3V to 5V +/- 10%
Human Body Model
PD# de-assertion
Industrial range
CONDITIONS
CONDITIONS
@ I
@ V
PULLUP
IN
OL
= GND, V
4
IN
= VDD
GND - 0.3
GND-0.5
MIN
-200
1.5
1.5
-40
2.1
2.7
10
33
30
-5
0
2
1
4
2000
MIN
-65
100.00
TYP
TYP
V
V
DD
V
MAX
1000
200
110
110
300
DDSMB
300
100
0.8
2.7
1.8
0.8
0.4
5.5
70
85
33
DD
5
7
5
6
3
5
5
+ 0.3
MAX
5.5V
150
125
4.6
4.6
+0.5V
UNITS NOTES
cycles
MHz
MHz
kHz
kHz
ms
mA
uA
uA
nH
pF
pF
pF
us
ns
ns
°C
°C
ns
ns
UNITS NOTES
V
V
V
V
V
V
°
°C
V
V
V
V
V
V
C
Datasheet
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1667C—04/20/11
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