89hpes4t4g2 Integrated Device Technology, 89hpes4t4g2 Datasheet
89hpes4t4g2
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89hpes4t4g2 Summary of contents
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... Device Overview The 89HPES4T4G2, a 4-lane 4-port Gen2 PCI Express® switch member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES4T4G2 is a peripheral chip that performs PCI Express base switching with a feature set optimized for servers, storage, communica- tions, and consumer applications ...
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... IDT 89HPES4T4G2 Data Sheet • Supports device power management states: D0 cold – Support for PCI Express Active State Power Management (ASPM) link state • Supports link power management states: L0, L0s, L1, L2/L3 Ready and L3 – Supports PCI Express Power Budgeting Capability – Configurable SerDes power consumption • ...
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... IDT 89HPES4T4G2 Data Sheet Processor SMBus PES4T4G2 Master SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES4T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura- tion, whenever the state of a Hot-Plug output needs to be modified, the PES4T4G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs ...
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... IDT 89HPES4T4G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES4T4G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level ...
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... IDT 89HPES4T4G2 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[7] GPIO[8] GPIO[9] GPIO[10] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. ...
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... IDT 89HPES4T4G2 Data Sheet Signal CCLKDS CCLKUS PERSTN SWMODE[2:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports ...
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... IDT 89HPES4T4G2 Data Sheet Signal REFRES0 REFRES1 REFRES2 REFRES3 V CORE PEA DD V PEHA DD V PETA Type Name/Description I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry kOhm +/- 1% resis- tor should be connected from this pin to ground. ...
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... IDT 89HPES4T4G2 Data Sheet Pin Characteristics Note: Some input pads of the PES4T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES4T4G2 Data Sheet Function SerDes Reference REFRES0 Resistors REFRES1 REFRES2 REFRES3 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. Schmitt Trigger Input (STI). Pin Name Type Buffer I/O Analog I/O I/O I/O Table 7 Pin Characteristics (Part ...
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... IDT 89HPES4T4G2 Data Sheet Logic Diagram — PES4T4G2 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 Master SMBus Interface Slave SMBus Interface System ...
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... IDT 89HPES4T4G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE T Falling edge rate C-FALL V Differential input high voltage ...
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... IDT 89HPES4T4G2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO- an Idle ordered set IDLE T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW T Minimum Instantaneous Lone Pulse Width ...
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... IDT 89HPES4T4G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state ...
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... IDT 89HPES4T4G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power DD V PETA PCI Express Transmitter Analog Voltage DD V Common ground SS 1 ...
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... IDT 89HPES4T4G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 12 (and also listed below) ...
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... IDT 89HPES4T4G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit V Differential peak-to-peak output TX-DIFFp-p voltage V Low-Drive Differential Peak to TX-DIFFp-p-LOW ...
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... IDT 89HPES4T4G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak- RX-DIFFp-p to-peak) RL Receiver Differential Return RX-DIFF Loss RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance RX-DIFF-DC (DC common mode impedance RX--DC Z Powered down input common RX-COMM-DC ...
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... IDT 89HPES4T4G2 Data Sheet I/O Type Parameter Description Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0. Gen Min Typ Max — — 8.5 — — — — — ...
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... IDT 89HPES4T4G2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES4T4G2 The following table lists the pin numbers and signal names for the PES4T4G2 device. Pin Function Alt Pin A1 V B17 I/O B18 I I ...
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... IDT 89HPES4T4G2 Data Sheet Pin Function Alt Pin H11 V K13 SS H12 V PEA K14 DD H13 V PEA K15 DD H14 NC K16 H15 NC K17 H16 V K18 SS H17 NC L1 H18 PEHA PEHA CORE ...
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... IDT 89HPES4T4G2 Data Sheet Pin Function Alt Pin U1 V U10 SS U2 PEREFCLKN U11 U3 V U12 U13 U5 NC U14 U6 REFRES1 U15 U7 NC U16 U8 PE1TN00 U17 U9 V U18 SS Alternate Signal Functions No Connection Pins NC Pins NC Pins B1 C18 B14 E5 B15 E14 ...
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... IDT 89HPES4T4G2 Data Sheet Power Pins V Core V Core G10 D14 G14 D15 G15 H10 E10 J8 E11 J10 E12 K4 E13 F10 K10 G4 K14 Core V I N15 G12 P6 A6 G13 P9 A10 H6 P12 ...
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... IDT 89HPES4T4G2 Data Sheet Ground Pins A11 A15 A16 B3 B16 C3 C6 C16 D16 D17 D18 G17 M16 E3 G18 E16 H11 N3 F3 H16 N13 F9 J11 N14 F11 J16 N16 F12 K3 N17 ...
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... IDT 89HPES4T4G2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBCLK MSMBDAT NO CONNECTION PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE1RN00 PE1RP00 PE1TN00 PE1TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 ...
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... IDT 89HPES4T4G2 Data Sheet Signal Name PEREFCLKN PEREFCLKP PERSTN REFRES0 REFRES1 REFRES2 REFRES3 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA, V PEHA PETA I/O Type Location D11 I/O V6 I/O U6 I/O K1 I/O K2 I D10 I B11 I C11 I/O, See Table 20 for a listing of power pins. ...
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... IDT 89HPES4T4G2 Data Sheet PES4T4G2 Pinout — Top View Core (Power I/O (Power PETA (Power PEA (Power) ...
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... IDT 89HPES4T4G2 Data Sheet PES4T4G2 Package Drawing — 324-Pin AL324/AR324 May 7, 2008 ...
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... IDT 89HPES4T4G2 Data Sheet PES4T4G2 Package Drawing — Page Two May 7, 2008 ...
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... IDT 89HPES4T4G2 Data Sheet Revision History April 24, 2008: Initial publication of Preliminary data sheet. May 7, 2008: Revised thermal values in Table 15. On Ordering Information page, changed package designations from RoHS to Green and silicon revision to ZB May 7, 2008 ...
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... IDT 89HPES4T4G2 Data Sheet Ordering Information NN A AAA Product Operating Device Product Family Family Voltage Detail Valid Combinations 89HPES4T4G2ZBAL 324-ball FCBGA package, Commercial Temperature 89HPES4T4G2ZBALG 324-ball Green FCBGA package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® ...