89hpes64h16 Integrated Device Technology, 89hpes64h16 Datasheet - Page 9

• Manufacturer Part Number: 89hpes64h16
• Description: 64-lane, 16-port Pcie System Interconnect Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES64H16 Data Sheet
P1011MERGEN
P1213MERGEN
P1415MERGEN
MSMBSMODE
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
Signal
GPIO[29]
GPIO[30]
GPIO[31]
Signal
CCLKDS
CCLKUS
Type
Type
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
Table 4 General Purpose I/O Pins (Part 4 of 4)
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a
single x8 port. The SerDes lanes associated with port 1 become lanes 4 through 7 of
port 0.
Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a
single x8 port. The SerDes lanes associated with port 3 become lanes 4 through 7 of
port 2.
Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a
single x8 port. The SerDes lanes associated with port 5 become lanes 4 through 7 of
port 4.
Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a
single x8 port. The SerDes lanes associated with port 7 become lanes 4 through 7 of
port 6.
Port 8 and 9 Merge. When this pin is asserted, port 9 is merged with port 8 to form a
single x8 port. The SerDes lanes associated with port 9 become lanes 4 through 7 of
port 8.
Port 10 and 11 Merge. When this pin is asserted, port 11 is merged with port 10 to
form a single x8 port. The SerDes lanes associated with port 11 become lanes 4
through 7 of port 10.
Port 12 and 13 Merge. When this pin is asserted, port 13 is merged with port 12 to
form a single x8 port. The SerDes lanes associated with port 13 become lanes 4
through 7 of port 12.
Port 14 and 15 Merge. When this pin is asserted, port 15 is merged with port 14 to
form a single x8 port. The SerDes lanes associated with port 15 become lanes 4
through 7 of port 14.
Table 5 System Pins (Part 1 of 2)
9 of 49
Name/Description
Name/Description
April 16, 2008