89hpes6t6g2 Integrated Device Technology, 89hpes6t6g2 Datasheet - Page 4

• Manufacturer Part Number: 89hpes6t6g2
• Description: 6-lane, 6-port Gen2 Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES6T6G2 Data Sheet
PEREFCLKP
PEREFCLKN
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
PE4RP[0]
PE4RN[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TN[0]
PE4TP[0]
PE5TP[0]
Signal
Signal
Signal
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[7]
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
Table 1 PCI Express Interface Pins (Part 2 of 2)
O
O
Table 3 General Purpose I/O Pins (Part 1 of 2)
I
I
I
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
Master SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the master SMBus which operates at 400 KHz.
Master SMBus Data. This bidirectional signal is used for data on the master
SMBus which operates at 400 KHz.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit
pair for port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit
pair for port 5.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is set at 100 MHz.
Table 2 SMBus Interface Pins
4 of 29
Name/Description
Name/Description
Name/Description
May 7, 2008