89hpes32t8 Integrated Device Technology, 89hpes32t8 Datasheet - Page 6

• Manufacturer Part Number: 89hpes32t8
• Description: 32-lane, 8-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89PES32T8 Data Sheet
SSMBADDR[5,3:1]
PEREFCLKN[2:1]
PEREFCLKP[2:1]
MSMBADDR[4:1]
PE7TP[3:0]
PE7TN[3:0]
MSMBCLK
MSMBDAT
REFCLKM
SSMBCLK
SSMBDAT
Signal
Signal
Type
Type
I/O
I/O
I/O
I/O
O
I
I
I
I
Table 2 PCI Express Interface Pins (Part 2 of 2)
PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
6 of 37
Name/Description
Name/Description
March 25, 2008