89hpes32h8 Integrated Device Technology, 89hpes32h8 Datasheet - Page 2

• Manufacturer Part Number: 89hpes32h8
• Description: 32-lane, 8-port Pcie System Interconnect Switch
• Manufacturer: Integrated Device Technology

Product Description
the most efficient system interconnect switching solution for applications
requiring maximum throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 128 Gbps of aggre-
gated, full-duplex switching capacity through 32 integrated serial lanes,
IDT 89HPES32H8 Data Sheet
Utilizing standard PCI Express interconnect, the PES32H8 provides
◆
◆
◆
◆
– Supports optional PCI Express end-to-end CRC checking
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
– Supports Hot-Swap
Power Management
– Supports PCI Power Management Interface specification,
– Unused SerDes disabled
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with
1mm ball spacing
Note: The configurations in the above diagram show the maximum port widths. The PES32H8 can negotiate to narrower port widths — x4,
x2, or x1.
• Compatible with Hot-Plug I/O expanders used on PC
• Supports powerdown modes at the link level (L0, L0s, L1,
Revision 1.1 (PCI-PM)
motherboards
L2/L3 Ready and L3) and at the device level (D0, D3
x8
2
3
Non-bifurcated
1 0
4 5
x8
x8
Figure 2 Port Configuration Examples
7
6
x8
hot
)
2 of 40
using proven and robust IDT technology. Each lane provides 2.5 Gbps
of bandwidth in both directions and is fully compliant with PCI Express
Base specification 1.1.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.1. The PES32H8 can operate either as a store and forward
or cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and two Virtual Channels
(VC) with sophisticated resource management to enable efficient
switching and I/O connectivity for servers, storage, and embedded appli-
cations.
SMBus Interface
provides full access to the configuration registers in the PES32H8,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES32H8 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the SMBus
address to which the device responds to be configured. In the master
interface, these address pins allow the SMBus address of the serial
configuration EEPROM from which data is loaded to be configured. The
SMBus address is set up on negation of PERSTN by sampling the
corresponding address pins. When the pins are sampled, the resulting
address is assigned as shown in Table 1.
x4
x4
The PES32H8 is based on a flexible and efficient layered architec-
The PES32H8 contains two SMBus interfaces. The slave interface
Six pins make up each of the two SMBus interfaces. These pins
2
3
Fully Bifurcated
4
1
x4
x4
5
0
x4
x4
7
6
x4
x4
April 16, 2008